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![Chapter 5: Tasks, Functions, and UDPs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-5
Task Definition and Calls
// port list style
task [automatic] task_identifier;
[declarations] // include arguments
procedural_statement
endtask
// port list declaration style
task [automatic] task_identifier ([argument_declarations]);
[other_declarations] // exclude arguments
procedural_statement
endtask
task [automatic] task_identifier(task_port_list); … endtask](https://image.slidesharecdn.com/14391970-250203033301-8277ba25/75/Tasks-and-UDP-s-in-verilog-coding14391970-ppt-5-2048.jpg)
![Chapter 5: Tasks, Functions, and UDPs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-6
A Task Example
// count the zeros in a byte
module zero_count_task (data, out);
input [7:0] data;
output reg [3:0] out;
always @(data)
count_0s_in_byte(data, out);
// task declaration from here
task count_0s_in_byte(input [7:0] data, output reg [3:0] count);
integer i;
begin // task body
count = 0;
for (i = 0; i <= 7; i = i + 1)
if (data[i] == 0) count= count + 1;
end endtask
endmodule](https://image.slidesharecdn.com/14391970-250203033301-8277ba25/75/Tasks-and-UDP-s-in-verilog-coding14391970-ppt-6-2048.jpg)
![Chapter 5: Tasks, Functions, and UDPs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-9
A Dynamic Task Example
// task definition starts from here
task automatic check_counter;
reg [3:0] count;
// the body of the task
begin
$display ($realtime,,"At the beginning of task, count = %d", count);
if (reset) begin
count = 0;
$display ($realtime,,"After reset, count = %d", count);
end
endmodule](https://image.slidesharecdn.com/14391970-250203033301-8277ba25/75/Tasks-and-UDP-s-in-verilog-coding14391970-ppt-9-2048.jpg)
![Chapter 5: Tasks, Functions, and UDPs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-11
Function Definition and Calls
// port list style
function [automatic] [signed] [range_or_type] function_identifier;
input_declaration
other_declarations
procedural_statement
endfunction
// port list declaration style
function [automatic] [signed] [range_or_type]
function_identifier (input_declarations);
other_declarations
procedural_statement
endfunction
function [automatic] [signed] [range_of_type] … endfunction](https://image.slidesharecdn.com/14391970-250203033301-8277ba25/75/Tasks-and-UDP-s-in-verilog-coding14391970-ppt-11-2048.jpg)
![Chapter 5: Tasks, Functions, and UDPs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-12
A Function Example
// count the zeros in a byte
module zero_count_function (data, out);
input [7:0] data;
output reg [3:0] out;
always @(data)
out = count_0s_in_byte(data);
// function declaration from here.
function [3:0] count_0s_in_byte(input [7:0] data);
integer i;
begin
count_0s_in_byte = 0;
for (i = 0; i <= 7; i = i + 1)
if (data[i] == 0) count_0s_in_byte = count_0s_in_byte + 1;
end
endfunction
endmodule](https://image.slidesharecdn.com/14391970-250203033301-8277ba25/75/Tasks-and-UDP-s-in-verilog-coding14391970-ppt-12-2048.jpg)
![Chapter 5: Tasks, Functions, and UDPs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-15
Automatic (Recursive) Functions
// the use of reentrant function
module factorial(input [7:0] n, output [15:0] result);
// instantiate the fact function
assign result = fact(7);
// define fact function
function automatic [15:0] fact;
input [7:0] N;
// the body of function
if (N == 1) fact = 1;
else fact = N * fact(N - 1);
endfunction
endmodule](https://image.slidesharecdn.com/14391970-250203033301-8277ba25/75/Tasks-and-UDP-s-in-verilog-coding14391970-ppt-15-2048.jpg)
![Chapter 5: Tasks, Functions, and UDPs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-16
Constant Functions
module RAM (addr_bus, data_bus);
parameter RAM_depth = 1024;
input [count_log_b2(RAM_depth)-1:0] addr_bus;
output reg [7:0] data_bus;
// function declaration from here
function integer count_log_b2(input integer depth);
begin // function body
count_log_b2 = 0;
while (depth) begin
count_log_b2 = count_log_b2 + 1;
depth = depth >> 1;
end
end
endfunction
endmodule](https://image.slidesharecdn.com/14391970-250203033301-8277ba25/75/Tasks-and-UDP-s-in-verilog-coding14391970-ppt-16-2048.jpg)
![Chapter 5: Tasks, Functions, and UDPs
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-32
Instantiation of UDPs
// an example of sequential UDP instantiations
module ripple_counter(clock, clear, q);
input clock, clear;
output [3:0] q;
// instantiate the T_FFs.
T_FF tff0(q[0], clock, clear);
T_FF tff1(q[1], q[0], clear);
T_FF tff2(q[2], q[1], clear);
T_FF tff3(q[3], q[2], clear);
endmodule](https://image.slidesharecdn.com/14391970-250203033301-8277ba25/75/Tasks-and-UDP-s-in-verilog-coding14391970-ppt-32-2048.jpg)
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- 1. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-1 Chapter 5: Tasks, Functions, and UDPs Department of Electronic Engineering National Taiwan University of Science and Technology Prof. Ming-Bo Lin
- 2. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-2 Syllabus Objectives Tasks Functions Combinational UDPs Sequential UDPs
- 3. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-3 Objectives After completing this chapter, you will be able to: Describe the features of tasks and functions Describe how to use tasks and functions Describe the features of dynamic tasks and functions Describe the features of UDPs (user-defined primitives) Describe how to use combinational and sequential UDPs
- 4. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-4 Syllabus Objectives Tasks Definition and call Types of tasks Functions Combinational UDPs Sequential UDPs
- 5. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-5 Task Definition and Calls // port list style task [automatic] task_identifier; [declarations] // include arguments procedural_statement endtask // port list declaration style task [automatic] task_identifier ([argument_declarations]); [other_declarations] // exclude arguments procedural_statement endtask task [automatic] task_identifier(task_port_list); … endtask
- 6. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-6 A Task Example // count the zeros in a byte module zero_count_task (data, out); input [7:0] data; output reg [3:0] out; always @(data) count_0s_in_byte(data, out); // task declaration from here task count_0s_in_byte(input [7:0] data, output reg [3:0] count); integer i; begin // task body count = 0; for (i = 0; i <= 7; i = i + 1) if (data[i] == 0) count= count + 1; end endtask endmodule
- 7. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-7 Syllabus Objectives Tasks Definition and call Types of tasks Functions Combinational UDPs Sequential UDPs
- 8. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-8 Types of Tasks (static) task task … endtask automatic (reentrant, dynamic) task task automatic … endtask
- 9. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-9 A Dynamic Task Example // task definition starts from here task automatic check_counter; reg [3:0] count; // the body of the task begin $display ($realtime,,"At the beginning of task, count = %d", count); if (reset) begin count = 0; $display ($realtime,,"After reset, count = %d", count); end endmodule
- 10. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-10 Syllabus Objectives Tasks Functions Definition and call Types of functions Combinational UDPs Sequential UDPs
- 11. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-11 Function Definition and Calls // port list style function [automatic] [signed] [range_or_type] function_identifier; input_declaration other_declarations procedural_statement endfunction // port list declaration style function [automatic] [signed] [range_or_type] function_identifier (input_declarations); other_declarations procedural_statement endfunction function [automatic] [signed] [range_of_type] … endfunction
- 12. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-12 A Function Example // count the zeros in a byte module zero_count_function (data, out); input [7:0] data; output reg [3:0] out; always @(data) out = count_0s_in_byte(data); // function declaration from here. function [3:0] count_0s_in_byte(input [7:0] data); integer i; begin count_0s_in_byte = 0; for (i = 0; i <= 7; i = i + 1) if (data[i] == 0) count_0s_in_byte = count_0s_in_byte + 1; end endfunction endmodule
- 13. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-13 Syllabus Objectives Tasks Functions Definition and call Types of functions Combinational UDPs Sequential UDPs
- 14. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-14 Types of Functions (static) function function … endfunction automatic (recursive, dynamic) function function automatic … endfunction
- 15. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-15 Automatic (Recursive) Functions // the use of reentrant function module factorial(input [7:0] n, output [15:0] result); // instantiate the fact function assign result = fact(7); // define fact function function automatic [15:0] fact; input [7:0] N; // the body of function if (N == 1) fact = 1; else fact = N * fact(N - 1); endfunction endmodule
- 16. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-16 Constant Functions module RAM (addr_bus, data_bus); parameter RAM_depth = 1024; input [count_log_b2(RAM_depth)-1:0] addr_bus; output reg [7:0] data_bus; // function declaration from here function integer count_log_b2(input integer depth); begin // function body count_log_b2 = 0; while (depth) begin count_log_b2 = count_log_b2 + 1; depth = depth >> 1; end end endfunction endmodule
- 17. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-17 Syllabus Objectives Tasks Functions Combinational UDPs Definition Instantiation Sequential UDPs
- 18. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-18 Definition of Combinational UDPs // port list style primitive udp_name(output_port, input_ports); output output_port; input input_ports; // UDP state table table // the state table starts from here <table rows> endtable endprimitive
- 19. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-19 Definition of Combinational UDPs State table entries The <input#> values must be in the same order as in the input list <input1><input2>……<inputn>:<output>;
- 20. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-20 A Primitive UDP --- An AND Gate primitive udp_and (out, a, b); output out; input a, b; table // a b : out; 0 0 : 0; 0 1 : 0; 1 0 : 0; 1 1 : 1; endtable endprimitive
- 21. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-21 Another UDP Example x y z f a b c g1 g2 g3 g4 primitive prog253 (output f, input x, y, z); table // truth table for f(x, y, z,) = ~(~(x | y) | ~x & z); // x y z : f 0 0 0 : 0; 0 0 1 : 0; 0 1 0 : 1; 0 1 1 : 0; 1 0 0 : 1; 1 0 1 : 1; 1 1 0 : 1; 1 1 1 : 1; endtable endprimitive
- 22. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-22 Shorthand Notation for Don’t Cares primitive udp_and(f, a, b); output f; input a, b; table // a b : f; 1 1 : 1; 0 ? : 0; ? 0 : 0; // ? expanded to 0, 1, x endtable endprimitive
- 23. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-23 Syllabus Objectives Tasks Functions Combinational UDPs Definition Instantiation Sequential UDPs
- 24. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-24 Instantiation of Combinational UDPs // instantiations of UDPs module UDP_full_adder(sum, cout, x, y, cin); output sum, cout; input x, y, cin; wire s1, c1, c2; // instantiate udp primitives udp_xor (s1, x, y); udp_and (c1, x, y); udp_xor (sum, s1, cin); udp_and (c2, s1, cin); udp_or (cout, c1, c2); endmodule
- 25. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-25 Syllabus Objectives Tasks Functions Combinational UDPs Sequential UDPs Definition Instantiation
- 26. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-26 Definition of Sequential UDPs // port list style primitive udp_name(output_port, input_ports); output output_port; input input_ports; reg output_port; // unique for sequential UDP initial output-port = expression; // optional for sequential UDP // UDP state table table // keyword to start the state table <table rows> endtable endprimitive
- 27. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-27 Definition of Sequential UDPs State table entries The output is always declared as a reg An initial statement can be used to initialize output <input1><input2>……<inputn>:<current_state>:<next_state>;
- 28. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-28 Level-Sensitive Sequential UDPs // define a level-sensitive latch using UDP primitive d_latch(q, d, gate, clear); output q; input d, gate, clear; reg q; initial q = 0; // initialize output q table // d gate clear : q : q+; ? ? 1 : ? : 0 ; // clear 1 1 0 : ? : 1 ; // latch q = 1 0 1 0 : ? : 0 ; // latch q = 0 ? 0 0 : ? : - ; // no change endtable endprimitive
- 29. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-29 Edge-Sensitive Sequential UDPs // define a positive-edge triggered T-type flip-flop using UDP primitive T_FF(q, clk, clear); output q; input clk, clear; reg q; // define the behavior of edge-triggered T_FF table // clk clear : q : q+; ? 1 : ? : 0 ; // asynchronous clear ? (10) : ? : - ; // ignore negative edge of clear (01) 0 : 1 : 0 ; // toggle at positive edge (01) 0 : 0 : 1 ; // of clk (1?) 0 : ? : - ; // ignore negative edge of clk endtable endprimitive
- 30. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-30 Shorthand Symbols for Using in UDPs
- 31. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-31 Syllabus Objectives Tasks Functions Combinational UDPs Sequential UDPs Definition Instantiation
- 32. Chapter 5: Tasks,Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 5-32 Instantiation of UDPs // an example of sequential UDP instantiations module ripple_counter(clock, clear, q); input clock, clear; output [3:0] q; // instantiate the T_FFs. T_FF tff0(q[0], clock, clear); T_FF tff1(q[1], q[0], clear); T_FF tff2(q[2], q[1], clear); T_FF tff3(q[3], q[2], clear); endmodule