IBM POWER8: The first OpenPOWER processor

IBM POWER8: The first OpenPOWER processor

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  POWER8: The first OpenPOWERprocessor Dr. Michael Gschwind Senior Technical Staff Member & Senior Manager IBM Power Systems Join the conversation at #OpenPOWERSummit 1 #OpenPOWERSummit
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  Why Power andWhy Now?  Power is optimized for server workloads  Power8 was optimized to simplify application porting  Power8 includes CAPI, the Coherent Accelerator Processor Interconnect • Building on a long history of IBM workload acceleration Join the conversation at #OpenPOWERSummit
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  4 POWER8 Processor Cores • 12cores (SMT8)  96 threads per chip • 2X internal data flows/queues • 64K data cache, 32K instruction cache Caches • 512 KB SRAM L2 / core • 96 MB eDRAM shared L3 • Up to 128 MB eDRAM L4 (off-chip) Accelerators • Crypto & memory expansion • Transactional Memory • VMM assist • Data Move / VM Mobility • Coherent Accelerator Processor Interface (CAPI) Join the conversation at #OpenPOWERSummit
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  5 POWER8 Core •Up toeight hardware threads per core (SMT8) •8 dispatch •10 issue •16 execution pipes: •2 FXU, 2 LSU, 2 LU, 4 FPU, 2 VMX, 1 Crypto, 1 DFU, 1 CR, 1 BR •Larger Issue queues (4 x 16-entry) •Larger global completion table •Larger Load/Store reorder queue •Improved branch prediction •Improved unaligned storage access •Improved data prefetch Join the conversation at #OpenPOWERSummit
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  6 POWER8 Architecture  High-performanceLE support – Foundation for a new ecosystem  Organic application growth – Instruction Fusion  Workload optimized – Power SIMD Extensions – Coherent Accelerator Processor Interface  Parallel programming productivity – Transactional Memory  Cloud ready – Cloud Mode – Reduced context switch overhead – Improved Interrupt performance  Dynamic System Optimization – Performance Monitoring – Dynamic Code Optimization 0 200 400 600 800 1000 1200 1400 1600 May-90 Oct-95 Apr-01 Oct-06 Apr-12 Sep-17 instructions Power evolution PowerPC Power ISA Join the conversation at #OpenPOWERSummit
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  Up to 2.7xperformance across key workloads vs. other 24-core Scale-Out Systems Join the conversation at #OpenPOWERSummit Source: Hot Chips 26
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  8 Acceleration with Vector-Scalar Execution Expand VSX beyond HPC  Memory to memory primitives – Exploit system bandwidth in apps & system  Coding support – AES, CRC, RAID,…  Business analytics – Numeric analytics algorithms – Structured & Unstructured Text Analytics  Database acceleration – Accelerate in-memory columnar DB Join the conversation at #OpenPOWERSummit
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  POWER8: expanding choicefor data formats  Big-Endian: Most Significant Byte First • Traditional enterprise server data format • The standard internet data format (“network byte order”) • Process five decades of database content • Protect investment into data storage and curation  Little-Endian: Least Significant Byte First • Traditional small system format (PC, mobile) • Participate in rich standard ecosystem • Simplify application portability for those seeking to upgrade to Power • High-volume hardware components often little-endian 3 2 1 0 0 1 2 3 Join the conversation at #OpenPOWERSummit
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  Workload-optimized acceleration with coherentaccelerators  Attached accelerators • Accelerate workloads with functions that are not a good fit for traditional general purpose CPU  Coherent integration in system architecture • Data sharing • Programming • Performance Join the conversation at #OpenPOWERSummit
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  Workload-optimized acceleration  On-chipintegrated accelerators (SoC design) • Compute accelerator (Cell BE) • Compression (P7+) • Encryption (P7+) • Random number generation (P7+) • …  SoC design offers highest integration, but… • New chip design to introduce new accelerator • Long time to market • Requires very high volumes Cell BE POWER7+ Join the conversation at #OpenPOWERSummit
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  CAPI: Coherent Accelerator ProcessorInterface  Integrate accelerators into system architecture with standardized, coherent protocol • CAPI functional protocol • PCIe signaling protocol  Modular interface enables third parties to provide high value-add components  Create workload-optimized innovative solutions • Faster time to market • Lower bar to entry • Variety of implementation options  FPGAs, ASICs Coherence Bus CAPP PSL POWER8 Join the conversation at #OpenPOWERSummit
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  CAPI accelerator programming CoherenceBus CAPP PSL Virtual Addressing • Accelerator can work with same virtual memory addresses that the processors use • CAPI shares page tables and provides address translation • Pointers de-referenced same as the host application • Peer-to-peer programming between CPU and accelerator with in-memory data sharing Hardware Managed Coherence • No need for memory pinning • Data fetched by accelerator based on accelerator application flow • Accelerator participates in locks • Low latency communication Join the conversation at #OpenPOWERSummit
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  Summary  POWER8 introducetraditional microarchitecture improvements • More Instruction level parallelism • More Data level parallelism • Larger caches and queues  Best-in-class systems performance for scale-out and scale-up  New foundational capabilities for OpenPOWER • High-performance little- and big-endian  Improved integration of industry standard ecosystem hardware  Improved application portability to OpenPOWER • CAPI enables system architects to extend processor capabilities  Create a broad range of workload optimized offerings Join the conversation at #OpenPOWERSummit
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  Join the conversationat #OpenPOWERSummit 15 © 2015 OpenPOWER Foundation Implementation / HPC / Research Software System / Integration I/O / Storage / Acceleration Boards / Systems Chip / SOC
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