An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

BOOM's Simulation Accelerator.

Unified open-source repository for OmniXtend protocol implementations in C, Verilog, and Chisel, supporting host and memory roles.

This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

An online viewer for Chipyard output files

😱 RoCC Accelerator Integration with Chipyard

This Github repository serves as a User Guide (UG) for new Chipyard users.