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1. ASIC_implementation_of_PULPino_SoC ASIC_implementation_of_PULPino_SoC Public

   My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

   Verilog 2

2. DSP_Custom_AXI_IPs DSP_Custom_AXI_IPs Public

   SystemVerilog 2

3. My_Verification_work My_Verification_work Public

   A repo for my System Verilog testbenches with test benches for UART, I2C, SPI, FIFOs and Bus protocols like AMBA, AHB and WISHBONE

   SystemVerilog 5 1

4. ASICs_Design_Diploma ASICs_Design_Diploma Public

   RTL to GDSII flow of a low Power configurable multi clock digital system

   Verilog 5 2

5. ODE_solver_NIOS_II ODE_solver_NIOS_II Public

   NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA

   Verilog