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IntelliJ Errors with Chisel 7.0.0-RC1 Despite Successful Compilation

Status: Open.

#4929 In chipsalliance/chisel;

· Emin017 opened on May 19, 2025

How to parse firrtl file/string to Circuit instance?

Status: Open.

#4899 In chipsalliance/chisel;

· canxin121 opened on Apr 20, 2025

Inaccrate Infomation in the "Get me Verilog" section of FAQ

Status: Open.

#4877 In chipsalliance/chisel;

· scratch-er opened on Apr 9, 2025

Warnings occurs when using the VCS backend for simulation in SVSIM

Status: Open.

#4848 In chipsalliance/chisel;

· jcvclouds opened on Apr 1, 2025

[svsim][chiselsim] Support Questa

Status: Open.

#4846 In chipsalliance/chisel;

· seldridge opened on Mar 31, 2025

ChiselSim not allowing capturing of stdout/stderr

Status: Open.

#4819 In chipsalliance/chisel;

· seldridge opened on Mar 21, 2025

Chisel drops escaped % in printf if it is the last character in the format string and preceded by a space

Status: Open.

#4818 In chipsalliance/chisel;

· jackkoenig opened on Mar 21, 2025

Mux Tree Generation

Status: Open.

#4809 In chipsalliance/chisel;

· escou64 opened on Mar 18, 2025

Bug in simulation verification

Status: Open.

#4791 In chipsalliance/chisel;

· tobias1012 opened on Mar 13, 2025

Error When Connecting Analog-Only Bundle to Verilog Blackbox

Status: Open.

#4775 In chipsalliance/chisel;

· ysljung opened on Mar 6, 2025

AddDedupGroupAnnotations creates invalid Annotations w/ Definition argument

Status: Open.

#4730 In chipsalliance/chisel;

· seldridge opened on Feb 25, 2025

Provide ChiselEnum Value for OneHot encoding

Status: Open.

#4729 In chipsalliance/chisel;

· hellow554 opened on Feb 25, 2025