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[feature request] Enhanced StreamWidthAdapter Supporting Non-Integer

Status: Open.

#1731 In SpinalHDL/SpinalHDL;

· hhucchenyixiao opened on May 14, 2025

TODO for the sync of scaladoc <-> SpinalDoc-RTD and doc improvement

Status: Open.

#1720 In SpinalHDL/SpinalHDL;

· mrcmry opened on Apr 30, 2025

A couple of minor TileLink Cache issues...

Status: Open.

#1716 In SpinalHDL/SpinalHDL;

· jtredux opened on Apr 26, 2025

Reusing precompile module for capturing simulation wave causes failure in Verilator backend

Status: Open.

#1714 In SpinalHDL/SpinalHDL;

· inochisa opened on Apr 24, 2025

[feature request] Some way to share constants between Spinal and Verilog/VHDL

Status: Open.

#1713 In SpinalHDL/SpinalHDL;

· thajohns opened on Apr 22, 2025

Scala 3 support

Status: Open.

#1710 In SpinalHDL/SpinalHDL;

· goekce opened on Apr 19, 2025

[Help] How to clone a nested bundle ?

Status: Open.

#1709 In SpinalHDL/SpinalHDL;

· facebreeze opened on Apr 17, 2025

[Issue] unexpected signal name

Status: Open.

#1704 In SpinalHDL/SpinalHDL;

· facebreeze opened on Apr 10, 2025

[RegIf]AxiLite4BusInterface: Wrong rdata when rready reply late

Status: Open.

#1693 In SpinalHDL/SpinalHDL;

· HaroldZ32 opened on Mar 27, 2025

Invalid stimulus data occurs during cross-clock domain simulation

Status: Open.

#1688 In SpinalHDL/SpinalHDL;

· buloruabutata opened on Mar 21, 2025

“emitFullComponentBindings = false” will generate wrong synt verrlog under some special case

Status: Open.

#1687 In SpinalHDL/SpinalHDL;

· Mido-sun opened on Mar 21, 2025

how to use [T <: Data] with dynamic width

Status: Open.

#1684 In SpinalHDL/SpinalHDL;

· buloruabutata opened on Mar 19, 2025