innovus

This repository presents a complete RTL-to-GDSII ASIC implementation of the PicoRV32 RISC-V processor using the Skywater 130nm (Sky130) open-source PDK. The project demonstrates an industry-standard VLSI backend flow using Cadence EDA tools, covering synthesis, placement, routing, verification, and GDSII generation.

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

Cardinal NIC and Chip Multiprocessor

ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.

Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.

An application using Cadence IC Package

DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino

This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.

Timing path visualization.

RISCV 32-bit Linux Processor

A complete ASIC design flow for a MNIST NPU. Features a quantized hardware-friendly architecture, SystemVerilog RTL implementation, and a verified backend-ready flow for logic synthesis and GDSII generation.

A high-performance, production-grade 64-bit RISC-V Multicore SoC ecosystem and industry-standard Cadence ASIC CAD flow (Genus/Innovus). Fully integrated 5-hart coherent core complex, TileLink interconnect, custom RoCC ML Systolic Array, PCIe, USB, HDMI, and silicon-proven IP blocks.

Simulation, Logical and Physical Syntesis of the RISC-V Steel Core using Cadence EDA tools.

This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC

Place and Route implementation of the previously completed RV32IM design using technology node 45 nm and Innovus Cadence

Detailed routed RT01 and other testcases with Innovus NanoRoute; includes RT01 random blockages. Example routes include CLK paths avoiding all blockages and connecting all DFF pins. All modules are designed with the GSCLK45nm standard cell library. Note that NanoRoute is typically used for routing std cell placements; in this case, custom top-level

A 16-lane SIMD GPU with 512-bit datapath, 4-warp scheduling, and scoreboard hazard detection — taped out on SCL 180nm as C2S0284

ASIC Physical Design implementation of a Secure Digital Door Lock using Verilog HDL, Cadence Genus, and Cadence Innovus.

public personal website

VHDL implementation and full digital ASIC physical design flow (45nm/7nm) for custom hardware modulo adders using Cadence Genus and Innovus.