System designing and modelling using fpga

System designing and modelling using fpga

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  INTERNATIONAL JOURNAL OFELECTRONICS AND International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 11, November (2014), pp. 47-52 © IAEME COMMUNICATION ENGINEERING TECHNOLOGY (IJECET) ISSN 0976 – 6464(Print) ISSN 0976 – 6472(Online) Volume 5, Issue 11, November (2014), pp. 47-52 © IAEME: http://www.iaeme.com/IJECET.asp Journal Impact Factor (2014): 7.2836 (Calculated by GISI)
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  47 IJECET © I A E M E SYSTEM DESIGNING AND MODELLING USING FPGA Prof. Abhinav V. Deshpande Assistant Professor, Department of Electronics Telecommunication Engineering, Prof. Ram Meghe Institute of Technology Research, Badnera, Amravati, Maharashtra, India ABSTRACT This paper presents the overview of an FPGA system in which different complex arithmetic and logical operations are performed by using a set of programmable and reconfigurable arrays of various logic gates and the task of performing a single operation is distributed equally to a set of given number of gates and the system is provided with a clock generator which provides the necessary timing and control to the system with the help of an external oscillator which is set to a given desired frequency. A set of instructions which is called as program is written to execute a certain task which is required to perform a single part of a given set of operations to be performed by the electronic circuit. The language of programming like Very High Speed Integrated Circuits Hardware Description Language (VHDL) and Verilog is used to program a logic gate like AND, OR, NOT, NAND, NOR, EX-OR gates and the study of different modules is done to understand the working of the programming language in order to gain preliminary knowledge about the syntax and instructions which constitute the base of any digital system. A basic knowledge about the language and its structured components like hardware modules and the commands is essential to acquire a general hold over the understanding of FPGA. Keywords: FPGA, PAL, PLA, CPLD, Array, AND Gate. 1. INTRODUCTION A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing– hence field programmable. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. As FPGA designs employ very fast I/Os and bidirectional data buses it becomes a challenge to verify correct timing of valid data within setup time and hold time. Floor
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  International Journal ofElectronics and Communication Engineering Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 11, November (2014), pp. 47-52 © IAEME planning enables resources allocation within FPGA to meet these time constraints. FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial reconfiguration of a portion of the design[1]and the low non-recurring 48 engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.[2] Figure 1: A FPGA from Altera Figure 2: FPGA from Xilinx FPGA’s contain programmable logic components called logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together– somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and OR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Figure 3: A Xilinx Zynq-7000 All Programmable System on a Chip 2. APPLICATIONS Technically speaking an FPGA can be used to solve any problem which is computable. This is trivially proven by the fact FPGA can be used to implement a Soft Microprocessor. Their advantage lies in that they are sometimes significantly faster for some applications due to their parallel nature and optimality in terms of the number of gates used for a certain process.
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  International Journal ofElectronics and Communication Engineering Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 11, November (2014), pp. 47-52 © IAEME 49 Specific applications of FPGAs include digital signal processing, software-defined radio, ASIC prototyping, medical imaging, image processing, speech recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal detection and a growing range of other areas. Common FPGA Applications: Aerospace and Defense Medical Electronics • Avionics/DO-254 • Communications • Missiles Munitions • Secure Solutions • Space ASIC Prototyping Audio • Connectivity Solutions • Portable Electronics • Radio • Digital Signal Processing (DSP) Consumer Electronics • Digital Displays • Digital Cameras • Multi-function Printers • Portable Electronics • Set-top Boxes Medical • Ultrasound • CT Scanner • MRI • X-ray • PET • Surgical Systems Security • Industrial Imaging • Secure Solutions • Image Processing Video Image Processing • High Resolution Video • Video Over IP Gateway • Digital Displays • Industrial Imaging
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  International Journal ofElectronics and Communication Engineering Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 11, November (2014), 3. ARCHITECTURE [2] consists of an array of logic blocks (called The most common FPGA architecture Configurable Logic Block, CLB, or Logic Array Block, LAB, depending on vendor), I/O pads, and routing channels. Generally, all the routing channels have the s Multiple I/O pads may fit into the height of one row or the width of one column in the array. An application circuit must be mapped into an FPGA with adequate resources. While the number of CLBs/LABs and I/Os required is easily routing tracks needed may vary considerably even among designs with the same amount of logic. For example, a crossbar switch requires much more routing than a systolic array with the same gate count. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of Lookup Tables (LUTs) and I/Os can be routed. This estimates such as those derived from Rent's rule or by experiments with existing designs. Figure 4: Simplified example illustration of a logic cell In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE, Slice etc.). A typical cell consists of a 4 below. The LUTs are in this figure split into two 3 into a 4-input LUT through the left mux. In selection of mode is programmed into the middle multiplexer. The output can be either synchronous or asynchronous, depending on the programming of the mux to the right, in the figure example. In practice, entire or parts of the FA are put as functions into the LUTs in order to save space. ALMs and Slices usually contains 2 or 4 structures similar to the example fig signals. CLBs/LABs typically contains a few ALMs/LEs/Slices. In recent years, manufacturers have started moving to 6 performance parts, claiming increased performance. Figure 5 pp. 47 50 same width (number of wires). determined from the design, the number of 4-input LUT, a Full Adder (FA) and a D-type flip 3-input LUTs. In normal mode arithmetic mode, their outputs are fed to the FA. The g 6-input LUTs in their high performance.[30] 5: Logic block pin locations – 7-52 © IAEME ame is determined by flip-flop as shown those are combined space.[27][28][29] figure, with some shared
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  International Journal ofElectronics and Communication Engineering Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 11, November (2014), pp. 47-52 © IAEME 51 Since clock signals (and often other high-fan out signals) are normally routed via special-purpose dedicated routing networks (i.e. global buffers) in commercial FPGAs, they and other signals are separately managed. Whenever a vertical and a horizontal channel intersect, there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure on the right illustrates the connections in a switch box. 4. FPGA DESIGN AND PROGRAMMING To define the behavior of the FPGA, the user provides a hardware description language (HDL) or a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. However, schematic entry can allow for easier visualisation of a design. Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place and route usually performed by the FPGA company's proprietary place-and-route software. The user will validate the map, place and route results via timing analysis simulation and other verification methodologies. Once the design and validation process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA. This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM. The most common HDLs are VHDL and Verilog although in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages there are moves to raise the abstraction level through the introduction of alternative languages. 5. CONCLUSION In this paper, a study of FPGA is presented with the theory and construction of an FPGA block and the method of manufacturing a logic block by using different types of logic gates and the basic building blocks of a PLA and the CPLD along with architecture of a PAL is described. The designing and modelling of a digital system by using FPGA's is discussed along with the applications of a digital block is presented. The programming of a FPGA is done with the help of VHDL and Verilog languages which are quite helpful in design and development of a digital system. This paper illustrates the beauty of designing and modelling of a FPGA with reference to it's functional blocks and component description. I think this will bring a novel revolution in the field of digital logic design. There is a huge demand for VHDL in the electronic engineering domain like industrial automation, intelligent transportation systems, smart design and digital logic circuits. 6. ACKNOWLEDGEMENTS I would like to thank the HOD, Department of Electronics Telecommunication Engineering, Prof. Ram Meghe Institute of Technology Research, Badnera, Amravati for providing me a nice platform for recognizing my research work and for giving me a opportunity to
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  International Journal ofElectronics and Communication Engineering Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 11, November (2014), pp. 47-52 © IAEME publish a research paper on the topic of FPGA design and development by using VHDL and Verilog as a part of Technical Education Quality improvement under the programme of TEQIP-2. 52 7. REFERENCES [1] Wisniewski, Remigiusz (2009). Synthesis of compositional microprogram control units for programmable devices. Zielona Góra: University of Zielona Góra. p. 153. ISBN 978-83- 7481-293-1. [2] FPGA Architecture for the Challenge [3] FPGA Signal Integrity tutorial [4] NASA: FPGA drive strength [5] Mike Thompson. Mixed-signal FPGAs provide GREEN POWER. EE Times, 2007-07-02. [6] History of FPGAs at the Wayback Machine (archived April 12, 2007) [7] Google Patent Search, Re-programmable PLA. Retrieved February 5, 2009. [8] Google Patent Search, Dynamic data re-programmable PLA. Retrieved February 5, 2009. [9] Peter Clarke, EE Times, Xilinx, ASIC Vendors Talk Licensing. June 22, 2001. Retrieved February 10, 2009. [10] Funding Universe. “Xilinx, Inc.” Retrieved January 15, 2009. [11] Clive Maxfield, Programmable Logic DesignLine, Xilinx unveil revolutionary 65nm FPGA architecture: the Virtex-5 family. May 15, 2006. Retrieved February 5, 2009. [12] Press Release, Xilinx Co-Founder Ross Freeman Honored as 2009 National Inventors Hall of Fame Inductee for Invention of FPGA [13] Maxfield, Clive (2004). The Design Warrior's Guide to FPGAs: Devices, Tools and Flows. Elsevier. p. 4. ISBN 978-0-7506-7604-5. [14] McConnel, Toni. EETimes. ESC - Xilinx All Programmable System on a Chip combines best of serial and parallel processing. April 28, 2010. Retrieved February 14, 2011. [15] Cheung, Ken, FPGA Blog. Xilinx Extensible Processing Platform for Embedded Systems. April 27, 2010. Retrieved February 14, 2011. [16] Nass, Rich, EETimes. Xilinx puts ARM core into its FPGAs. April 27, 2010. Retrieved February 14, 2011. [17] Leibson, Steve, Design-Reuse. Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform - Part 1. May. 03, 2010. Retrieved February 15, 2011. [18] Wilson, Richard, Electronics Weekly. Xilinx acquires ESL firm to make FPGAs easier to use. January 31, 2011. Retrieved February 15, 2011. [19] Dylan McGrath, EE Times, FPGA Market to Pass $2.7 Billion by '10, In-Stat Says. May 24, 2006. Retrieved February 5, 2009. [20] Dylan McGrath, EE Times, Gartner Dataquest Analyst Gives ASIC, FPGA Markets Clean Bill of Health. June 13, 2005. Retrieved February 5, 2009. [21] Naga Raju Boya, Sreelekha Kande, Vijay Kumar Jinde, Swapna Chintakunta, Mahesh Ungarala and Ramanjappa Thogata, “Design and Development of FPGA Based Temperature Measurement and Control System”, International Journal of Electronics and Communication Engineering Technology (IJECET), Volume 4, Issue 4, 2013, pp. 86 - 95, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. [22] G.Prasad and N.Vasantha, “Design and Implementation of Multi Channel Frame Synchronization in FPGA”, International Journal of Electronics and Communication Engineering Technology (IJECET), Volume 4, Issue 1, 2013, pp. 189 - 199, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.