Finfet Transistors

Finfet Transistors

• 1.
  FINFET TRANSISTORS BY: ESMAEILJAVADI MASTER STUDENT OF KNTU 1
• 2.
  MOOR’S LAW • 1965– 1975 first edition Theory • Review in 1975 until now • 6m from 1976 to 7nm in 2019 2
• 3.
  HISTORY • 20nm Featuresize challenge in integration • DIBL, Constriction Doping, Vth, Quantionic reactions, … • FINFET Theory, Revolution in Structure of Planar Transistors • HU & King-Liu & BOKO from Berkeley California firs theorist of FINFET 3
• 4.
  MOSFET SHORT CHANNELEFFECTS • Cg-s & Cg-d & Cg-ch • Punch – Through & Doping • DIBL Effect • Surface Current Effect 4
• 5.
  SOI MOSFET STRUCTURE •Using SOI Wafer • Advantage : • Reduce the parasitic junction capacitance • Lower power • Disadvantage : • Difficulty in manufacturing • Self-heating problem 5
• 6.
  FINFET THEORY &STRUCTURE • Offer in 1999 - 2000 • Without doping • Improve channel control • Decrease channel length • Increase L/W parameter 6
• 7.
  CHANNEL IMPROVING Width ofChannel = 2 X Fin Height + Fin Width (Equation-4) 7
• 8.
  FINFET OPERATION 8
• 9.
  ADVANTAGE FINFET ADVANTAGES • Solvedisadvantage parameter in MOSFETs. • Feature sizes - Possible to lower 7nm. • Much lower power consumption allows high integration levels. (150%) • Operating speed - Often in excess of 30% faster. • Static leakage current-Typically reduced by up to 90% 9
• 10.
  SAMSUNG FOUNDRY'S NEWTRANSISTOR 7nm Samsung Technology : • GEAT-ALL-AROUND FET TRANSISTOR (GAAFET) • MULTI-BRIDGE-CHANNEL FET TRANSISTOR (MBCFET) 10
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  THE END 11