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Critical Performance Metrics for DDR4 based Systems
The document discusses critical performance metrics for DDR4 systems, focusing on how to effectively monitor memory performance without impacting system functionality. It introduces traditional and new performance metrics, emphasizes the importance of power management, bandwidth, and latency, and highlights methods for analyzing memory performance, such as page hit analysis and bank utilization. The insights gathered aim to foster better memory controller designs and optimize performance while addressing challenges like row hammer detection.
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Critical Performance Metrics for DDR4 based Systems
- 1. CRITICAL MEMORY PERFORMANCE METRICSFOR DDR4 SYSTEMS Barbara Aichinger Vice President New Business Development FuturePlus Systems Corporation
- 2. Outline • How canwe monitor the very fast low voltage DDR4 memory without effecting the system? • Traditional Performance Metrics – Bandwidth, Latency and Power Management • New Performance Metrics – Bus Mode Analysis – Page Hit Analysis – Multiple Open Banks Analysis – Bank Utilization Analysis – Row Hammer (excessive Activate) Detection • Measured DDR4 Performance in a real target
- 3. How to Monitorthe DDR4 Memory • Use a slot interposer to ‘listen’ to the traffic between the DIMM and the Memory Controller – A small amount of current is ‘tapped’ off the bus – Only the Address, Command and Control bus needs to be monitored – Same probing method can be used for SODIMM and ‘memory down’ using a BGA adapter
- 4.
- 5. Monitoring the DDR4Memory • Highly attenuated signals are then amplified and the bus is ‘replicated’ inside the equipment
- 6. The system bootsand runs never knowing the equipment is present
- 7. Performance Metrics • Billionsof clock cycles every second • Old methods of measurement captures small amount of time in large trace buffers • New method uses sophisticated event counters to: – Never miss a clock cycle – Count Performance Metrics for long periods of time REAL TIME
- 8. Work Smarter notHarder • For Performance metrics the DDR Detective® uses counters instead the traditional trace memory – To capture a second of DDR4 traffic would take 4.5Gbytes of logic analyzer/protocol analyzer trace depth $$$$! • 1 hour = 270 Gbytes of trace depth and then time to sift through it and post process! – By using large counters and counting events and the time between events we can achieve hours and days worth of metrics with no trace buffer memory and with no time consuming post processing
- 9. 4 Memory Channels each channel is2 slots ASUS X99 DDR4 Motherboard
- 10. Traditional Measurements • Bandwidth –Command Bus Utilization – Data Bus Utilization • Power Management • Latency
- 11. Bandwidth • Overhead – Anyuse of the bus other than a Read or a Write – Command Bus Utilization • Data Bus – Utilization: the % of the time that Read or Write Data is being transferred – Bandwidth: the amount of data transferred per second
- 12.
- 13. Command Bus Utilization ACT 4%PRE 4% RD-BL8 7% WR-BL8 4% PREA 0% REF 0%ZQCS 0% DES 81%
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- 18. Power Managementwhile runningGoogle StressApp
- 19. Power Management AnalysisUbuntuBoot Embedded Video
- 20. Power Management • ~50Mservers Servers World Wide • Each Server averages 16-24 DIMMs – 800M to 1.2B DIMMs • Even small power savings per DIMM can add up Every time Facebook’s data center engineers figure out a way to reduce server consumption by a single watt, the improvement, at Facebook’s scale, has the potential to add millions of dollars to the company’s bottom line. Yevgeny Sverdlik Editor in Chief Data Center Knowledge
- 21. Latency • Several JedecParamters apply: – RD to WR same rank tSR_RTW – RD to PRE/PREA same Rank tRTP – WR to PRE(SB) or PREA (SR) tWR – Read to Read different Rank tDR_RTR – Read to Write different Rank DR_RTW – Write to Read different Rank tDR_WTR – Write to Write different Rank tDR_WTW
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- 23. Latency Measurements measurement madeat 1867 V# Parameter Description Spec Measured V2 tSR_RTW RD to WR same Rank 8 10 V11 tRTP RD to PRE same Rank 8 8 V12 tWR WR to PRE SB or PREA SR 31 31 V53 tDR_RTR RD to RD diff Rank 5 6 V57 tDR_WTR WR to RD diff Rank 3 6 V59 tDR_WTW WR to WR diff Rank 5 8
- 24.
- 25. Latency Measurements V# ParameterDescription Spec Measured V1 tCCD_L RD to RD Same Bank Group 5 6 V3 tCCD_L WR to WR Same Bank Group 5 6 V4 tCCD_S RD to RD diff Bank Group 4 4 V5 tCCD_S WR to WR diff Bank Group 4 4 V6 tRRD_L ACT to ACT Same Bank Group 5 5 V7 tWTR_L ACT to ACT diff Bank Group 4 4 V9 tWTR_L WR to RD Same Bank Group 22 23 V10 tWTR_S WR to RD Diff Bank Group 17 19
- 26. Latency • Good designsoperate on the edge of the spec • Architectural tradeoffs will occur • Do I need margin? – Design for the worst case and buy quality parts
- 27. New Performance Metrics •Page Hit Analysis – Read Hit: Page was Open – Read Miss : Page was not Open, Transaction was preceded by an ACT – Write Hit: Page was Open – Write Miss: Page was not Open, Transaction was preceded by an ACT – Unused: Page was opened and closed and never accessed • Multiple Open Banks – Open Banks make for faster access IF your going to that bank on the next access…performance hit if your not – Power hit when banks are open • Bank Group Analysis – New for DDR4: Back to back access to same bank is a performance hit – Faster to have back to back accesses to different bank groups
- 28. Ubuntu Boot @2133
- 29.
- 30. Multiple Open Banks Howmany are open at any one time 0 4 8
- 31. Bank Group AccessAnalysis • tCCD_L – Takes longer for back to back RD/WR accesses to the same bank group • tCCD_S – Can reduce latency by going to different bank groups
- 32. Bank Group AccessAnalysis Relative to the previous transaction how many times did the following transaction go to the same/different bank group
- 33. More Performance Metrics! •Bank Utilization – What happens during a chip kill or page retirement scenario? – How does the traffic reallocate? – What are the performance implications? • Do I have system hot spots? – Row Hammer (excessive Activates) • Fast Boot – Why does the system take so long to boot?
- 34. Bank Utilization Percentage oftotal cycles the banks are open (running Google Stress App)
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- 36.
- 37. Row Hammer Excessive ACTIVATEcommands to a single Row • An identified failure mechanism in DDR3 memory • The result of charge leakage • Current work around is to increase the refresh rate – Burns power, lowers performance – Lowers the statistical probability of an error
- 38. Critical Applications cannot tolerateRow Hammer failures • Memory Vendors are specifying how many ACTIVATES per Retention cycle to a single row the memory can tolerate • However there is no way the memory controller or the memory can count this • Critical Software applications should be tested to ensure that the Row Hammer Threshold is not reached
- 39. One method todetect Row Hammer
- 40. Detecting Excessive ACTIVATECommands
- 41. Critical DDR4 PerformanceMetrics • Memory Controller/System Architecture – Can this insight lead to better designs? – Benchmark Servers Memory Performance • Workload Analysis – Should the Memory Controller settings be based on criteria set by the workload? – Can compilers be made better? – Can critical applications be written to avoid Row Hammer? • Do we all need a DDR5? – Work Smarter not Harder and understand what we have
- 42. Summary • Power Management,Bandwidth, Latency • NEW Metrics: – Page Hit Analysis – Multiple Open Banks – Bank Group Analysis – Bank Utilization – Boot Analysis – Row Hammer Detection – New Measurements give insight into new designs and better architectures
- 43. Contact Information Barbara Aichinger VicePresident New Business Development FuturePlus Systems [email protected] www.FuturePlus.com Check out our new website dedicated to DDR Memory! www.DDRDetective.com