Prof. Neeraj Bhargava
Mrs. Pooja Dixit
Department of Computer Science, School of Engineering
& System Sciences
MDS University Ajmer, Rajasthan
 Combinational circuit is a circuit in which we combine the different
gates in the circuit, for example encoder, decoder, multiplexer and
demultiplexer. Some of the characteristics of combinational circuits
are following −
 The output of combinational circuit is depends upon combination of
input variables.
 The combinational circuit do not use any memory. The previous state
of input does not have any effect on the present state of the circuit.
 A combinational circuit can have an n number of inputs and m
number of outputs.
Block diagram
 Observe the problem definition.
 Determine the required input and output variable.
 Assign letters (r) symbols to the input variable.
 Make truth table that define required relationship.
 Determine the simplified boolean expression using K-Map.
 Draw logic diagram.
Example:
 Design a Combination Circuit with two inputs which produce output
as logic 0 when any one input is one.
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
1
 Half adder is a combinational logic circuit with two inputs and two
outputs.
 The half adder circuit is designed to add two single bit binary
number A and B.
 It is the basic building block for addition of two single bit numbers.
This circuit has two outputs carry and sum.
Block diagram
 A Half-adder circuit needs two binary inputs and two binary outputs.
The input variable shows the augend and addend bits whereas the
output variable produces the sum and carry. We can understand the
function of a half-adder by formulating a truth table. The truth table
for a half-adder is:
 'x' and 'y' are the two inputs, and S (Sum) and C (Carry) are the two
outputs.
 The Carry output is '0' unless both the inputs are 1.
 'S' represents the least significant bit of the sum.
 The simplified sum of products (SOP) expressions is:
 S = x'y+xy', C = xy
 Half Adder is a combinational logic circuit which is designed by
connecting one EX-OR gate and one AND gate. The half adder
circuit has two inputs: A and B, which add two input digits and
generates a carry and a sum.
 The logic diagram for a half-adder circuit can be represented as:
 Full adder is developed to overcome the drawback of Half Adder
circuit. It can add two one-bit numbers A and B, and carry c. The full
adder is a three input and two output combinational circuit.
 Block diagram
 Truth Table
 Two of the input variable 'x' and 'y',
represent the two significant bits to be added.
 The third input variable 'z', represents the
carry from the previous lower significant
position.
• The outputs are designated by the symbol
'S' for sum and 'C' for carry.
• The eight rows under the input variables
designate all possible combinations of 0's,
and 1's that these variables may have.
• The input-output logical relationship of the
full-adder circuit may be expressed in two
Boolean functions, one for each output
variable.
• Each output Boolean function can be
simplified by using a unique map method.
 Circuit Diagram

Combinational circuit.pptx

  • 1.
    Prof. Neeraj Bhargava Mrs.Pooja Dixit Department of Computer Science, School of Engineering & System Sciences MDS University Ajmer, Rajasthan
  • 2.
     Combinational circuitis a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits are following −  The output of combinational circuit is depends upon combination of input variables.  The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit.  A combinational circuit can have an n number of inputs and m number of outputs. Block diagram
  • 3.
     Observe theproblem definition.  Determine the required input and output variable.  Assign letters (r) symbols to the input variable.  Make truth table that define required relationship.  Determine the simplified boolean expression using K-Map.  Draw logic diagram. Example:  Design a Combination Circuit with two inputs which produce output as logic 0 when any one input is one. A B Y 0 0 1 0 1 0 1 0 0 1 1 0 1
  • 4.
     Half adderis a combinational logic circuit with two inputs and two outputs.  The half adder circuit is designed to add two single bit binary number A and B.  It is the basic building block for addition of two single bit numbers. This circuit has two outputs carry and sum. Block diagram
  • 5.
     A Half-addercircuit needs two binary inputs and two binary outputs. The input variable shows the augend and addend bits whereas the output variable produces the sum and carry. We can understand the function of a half-adder by formulating a truth table. The truth table for a half-adder is:  'x' and 'y' are the two inputs, and S (Sum) and C (Carry) are the two outputs.  The Carry output is '0' unless both the inputs are 1.  'S' represents the least significant bit of the sum.
  • 6.
     The simplifiedsum of products (SOP) expressions is:  S = x'y+xy', C = xy  Half Adder is a combinational logic circuit which is designed by connecting one EX-OR gate and one AND gate. The half adder circuit has two inputs: A and B, which add two input digits and generates a carry and a sum.  The logic diagram for a half-adder circuit can be represented as:
  • 7.
     Full adderis developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and carry c. The full adder is a three input and two output combinational circuit.  Block diagram
  • 8.
     Truth Table Two of the input variable 'x' and 'y', represent the two significant bits to be added.  The third input variable 'z', represents the carry from the previous lower significant position. • The outputs are designated by the symbol 'S' for sum and 'C' for carry. • The eight rows under the input variables designate all possible combinations of 0's, and 1's that these variables may have. • The input-output logical relationship of the full-adder circuit may be expressed in two Boolean functions, one for each output variable. • Each output Boolean function can be simplified by using a unique map method.
  • 9.