7 Interrupt.ppt

7 Interrupt.ppt

• 1.
  1 Interrupt Instructions  TheBOUND instruction, which has two operands, compares a register with two words of memory data.  For example, if the instruction BOUND AX,DATA is executed, AX is compared with the contents of DATA and DATA+ 1 and also with DATA+2 and DATA+3. If AX is less than the contents of DATA and DATA+1, 'a type 5 interrupt occurs. If AX is greater than DATA+2 and DATA+3, a type 5 interrupt occurs. If AX is within the bounds of these two memory words, no interrupt occurs.
• 2.
  2 Interrupt Instructions (cont.) The INTO instruction checks the overflow flag (OF). If OF 1, the INTO instruction calls the procedure whose address is stored in interrupt vector type number 4. If OF = 0, then the INTO instruction performs no operation and the next sequential instruction in the program executes.
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  3 Interrupt Instructions (cont.) The INT n instruction calls the interrupt service procedure that begins at the address represented in vector number n.  For example, an INT 80H call the interrupt service procedure whose address is stored in vector type number 80H (00020OH-00203H).  To determine the vector address, just multiply the vector type number (n) by 4. This gives the beginning address of the 4-byte long interrupt vector.  For example, an INT 5 = 4 x 5 or 20 (14H). The vector for INT 5 begins at address 000014H and continues to 000017H.
• 4.
  4 Interrupt Instructions (cont.) The IRET instruction is a special return instruction used to return for both software and hardware interrupts.  The IRET instruction is much like a normal far RET, because it retrieves the return address from the stack. It is unlike the normal return because it also retrieves a copy of the flag register from the stack.
• 5.
  5 HARDWARE INTERRUPTS  Themicroprocessor has two hardware interrupt inputs: non-maskable interrupt (NMI) and interrupt request (INTR).  Whenever the NMI input is activated, a type 2 interrupt occurs because NMI is internally decoded.  The INTR input must be externally decoded to select a vector. Any interrupt vector can be chosen for the INTR pin, but we usually use an interrupt type number between 20H and FFH.
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  6 The non-maskable interrupt NMI is an edge-triggered input that requests an interrupt on the positive edge (0-to- 1 transition). After a positive edge, the NMI pin must remain a logic 1 until it is recognized by the microprocessor.  Note that before the positive edge is recognized, the NMI pin must be a logic 0 for at least two clocking periods.  The NMI input is often used for parity errors and other major system faults such as power failures.
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  7 Power Failure DetectionCircuit The interrupt service procedure, stores the contents of all internal registers and other data into a battery backed-up memory.
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  8 Power Failure DetectionCircuit (Cont.)  When DC power fails, the battery provides a reduced voltage to the VCC connection on the memory device. Most memory devices will retain data with VCC voltages as low as 1.5V so the battery voltage does not need to be +5.0V.
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  9 The interrupt requestinput  INTR is level-sensitive, which means that it must be held at a logic 1 level until it is recognized.  The INTR pin is set by an external event and cleared inside the interrupt service procedure. This input is automatically disabled once it is accepted by the microprocessor and re-enabled by the IRET instruction at the end of the interrupt service procedure.  Ile microprocessor responds to the INTR input by pulsing the INTA output in anticipation of receiving an interrupt vector type number on data bus connection D7-D0.
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  10 The interrupt requestinput (Cont.)  A simple circuit that applies interrupt vector type number FFH to the data bus in response to an INTR.  Notice that the INTA pin is not connected in this circuit. Because resistors are used to pull the data bus connections (D0-D7 ) high, the microprocessor automatically sees vector type number FFH in response to the INTR input.
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  11 Using a Three-stateBuffer for INTA  Figure shows how interrupt vector type number 80H is applied to the data bus (D0-D7 ) in response to an INTR.  The octal buffer applies the interrupt vector type number to the data bus in response to the INTA pulse.  The vector type number is easily changed with the DIP switches that are shown in this illustration.
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  12 Making the INTRInput Edge-triggered.  Often we need an edge triggered input instead of a level-sensitive input.  Here the clock input becomes an edge triggered interrupt request input, and the clear input is used to clear the request when the INTA signal is output by the microprocessor.  Also note that the RESET signal initially clears the flip-flop so that no interrupt is requested when the system is first powered.
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