Early PA-RISC Systems
Information on these very early models and their details is sometimes quite incoherent.
This includes HP documentation (both sales and technical), which not always describe the processor and system
features of these computers coherently. In some cases, the system type was deduced — from
supplied system block diagrams together with MIPS benchmarks.
Computers names and model numbers were also compiled from various sources and may be not completely
correct.1
840: First PA-RISC Server, TS-1 (TTL)2
The first commercial PA-RISC product appeared in 1986 with the HP 9000/840 (Indigo) computer, based on a six-board TTL implementation of the 32-bit PA-RISC 1.0 architecture, TS-1, running at 8 MHz. The TTL boards measure 8.4�11.3″, SRAMs/PALs and about 150 ICs each. The TS-1 boards implement the processor pipeline, a 4096-entry TLB and 128 KB (L1) cache, divided into 64 KB for each data and instruction.
Two main buses are used in the I/O system:
- Central Bus (CTB — also called MidBus) connects the processor to the main memory and the secondary I/O bus (see below). CTB is 32-bit wide and has a clock speed of 8 MHz, with a sustained transfer rate of 20 MB/s. Seven slots for general purpose I/O cards are available.
- Channel I/O (CIO) is the central device I/O bus. Up to three CIO buses (also called CIBs) are supported in a single 9000/840 computer. (Others mention only one CIO channel on the 9000/840 — all three channels apparently were reserved for the very similar HP 3000/930.) CIO/CIB is 16-bit wide and achieves a transfer rate of 5 MB/s with a clock speed of 4 MHz. Seven (shared) I/O slots are available. Supported devices on CIO include HP-IB (Hewlett-Packard Interface-Bus, commonly used for instrumentation and measurement devices) and networking adapters.
Seven shared slots for I/O and memory are available, for up to 112 MB of RAM (7�16 MB; 2-16 MB memory modules were supported). The optional graphics adapter used one I/O and one memory slot, reducing the maximum RAM to 96 MB. Included by default into the system is a separate Floating Point Coprocessor (FPC) board. The 840 could be upgraded via a CPU board swap to 825, 835 or 845s retaining the case and memory and I/O boards.
It achieved about 4.5 MIPS and ran HP-UX version 1.0 (heavily BSD-based) up until version 10.01 (the pre-Y2k release). Storage and media devices were attached to the HP-IB bus, SCSI was only later (and with newer boot ROMs) available.
825, 835 and 850: NS-1 (NMOS)
One year later, 1987, first systems with 32-bit PA-RISC 1.0 processors implemented in NMOS-III logic, the PA-RISC NS-1, appeared:3
HP 9000/825 FireFox (also HP 9000/825S):
- 25 MHz NS-1 processor on two boards
- 16 KB cache
- 2048-entry TLB
- CTBs run at 8.33 MHz
- Maximum RAM of 112 MB (7�16 MB), 96 MB (6�16 MB) with graphics adapter
- Seven shared I/O (CIO) and memory slots
- Performance of about 9 MIPS
- Price of about US $42,500 at time of introduction
- Also sold with graphics hardware (825CHX included 2D adapter, 825SRX up to 24-bit 3D graphics)
HP 9000/835 TopGun (also HP 9000/835S):
- 30 MHz NS-1 processor (Not completely clear if the 835 is really based on a NS-1 — performance figures (MIPS) and clock speed (all NS-2 have a maximum of 27.5 MHz while the 835 has a CPU speed of 30 MHz) point to a NS-1 while system diagrams point to a NS-2)
- 128 KB cache
- 4096-entry TLB
- CTBs run at 10 MHz (their maximum)
- Maximum RAM of 112 MB (7�16 MB), 96 MB (6�16 MB) with graphics adapter
- Seven shared I/O (CIO) and memory slots
- Performance of about 14 MIPS
- Price of about US $45,000 at time of introduction
- Also sold with graphics hardware (835CHX included 2D adapter, 835SRX up to 24-bit 3D graphics)
- The 9000/834 was the same as a standard 835 however with a two-user limit
- The 9000/835SE is a high-end version with integrated CIO expander
- Server version (without graphics) shortly sold as 9000/635SV
- A port of early PA-RISC HPBSD ran on 834 and 835, as did an (unreleased) Mach 3.0 port (not the Mach 4/Lites for 700s workstations) from the University of Utah
- A in-progress port of the Chorus operating system (v3.3 nucleus — kernel — and v3.2 MiX — the operating system personality on top) was ported in 1990-1991 to the 834
HP 9000/850 Cheetah (also HP 9000/850S):
- 27.5 MHz NS-1 processor
- 128 KB cache (combined I/D)
- 4096-entry TLB
- CTBs run at 9.16 MHz
- CIO I/O bus
- Maximum RAM of 128 MB with one memory controller (MC0) and 256 MB with two memory controllers (MC0, MC1) [it could be the 256 MB/two MCs were only supported on the HP 3000 equivalents]
- Performance of about 14 MIPS
- Price of about US $200,000 at time of introduction
RAM could be expanded with 16 MB memory arrays, i.e., memory boards.
The systems use three main buses, expanding the original 9000/840 architecture:4
- The 64-bit wide System Main Bus (SMB) connects the CPU, main memory and I/O (over CTBs) with a throughput of 100 MB/s.
- Two CTBs/Midbuses (see Central Bus in the TS-1/TTL section) attach via two bus converters to the SMB
- In turn, the rest of the I/O devices are attached via CIO/CIBs (see Channel I/O above) to the two CTBs.
- The 850 additionally features two Memory Array Buses (MABs — MAB-0 and MAB-1), capable of linking up eight 16 MB memory modules (arrays) via a 72-bit datapath the the SMB.
Earlier versions of this page listed four models as having a NS-1 CPU; however after careful review the 845 was moved to the NS-2 group of servers.
845, 855 and 860: NS-2 (NMOS)
Later, in 1989, similar computers based on the NS-2, a revamped NS-1, appeared (from early 1989 till late 1990). The later PA-RISC 1.0 and CIO bus based servers include:5
HP 9000/845 ShoGun:
- 27.5 MHz NS-2 processor (not completely clear if this system is in fact based on a NS-1 or NS-2 — performance figures (MIPS) and cache/TLB sizes point to the latter)
- 256 KB cache
- 16384-entry TLB
- CTBs run at 9.16 MHz
- Maximum RAM of 112 MB (7�16 MB), 96 MB (6�16 MB) with graphics adapter
- Seven shared I/O (CIO) and memory slots
- Performance of about 22 MIPS
- Server version (without graphics) shortly sold as 9000/645SV
HP 9000/855 Jaguar (also HP 9000/855S):
- 27.5 MHz NS-2 processor
- 256 KB cache (separate I/D)
- 16384-entry TLB
- CTBs run at 9.16 MHz
- Maximum RAM of 128 MB with one memory controller (MC0) and 256 MB with two memory controllers (MC0, MC1) [it could be that 256 MB/two MCs were only supported on the HP 3000 equivalents]
- Performance of about 22 MIPS
- Price of about US $300,000 at time of introduction
HP 9000/860 (also HP 9000/860S) Cougar:
- 27.5 MHz NS-2 processor
- 1024 KB cache (separate I/D)
- 16384-entry TLB
- CTBs run at 9.16 MHz
- Maximum RAM of 128 MB with one memory controller (MC0) and 256 MB with two memory controllers (MC0, MC1) [it could be the 256 MB/two MCs were only supported on the HP 3000 equivalents]
These systems are all based on the same I/O architecture and CIO devices and faciliate the same CPU design — PA-RISC 1.0 NS-2. The 860 could be upgraded with newer CPU boards to a 865 or 870 (see below).
865 and 870: PCX (CMOS)
The 9000/865 and the multi-processor 9000/870 (the first PA-RISC SMP system) include the first PA-RISC processors implemented in CMOS — the PA-RISC 1.0 PCX. These systems are very similar to the NS-2 based servers (with the 860 being board-upgradeable to a 865 or 870) and feature the same principal system and I/O architecture (with a slightly modified CPU/SPU architecture).6 These system use the same 16 MB memory arrays as earlier servers but could additionally use 64 MB boards.
HP 9000/865 Panther:
- 50 MHz PCX processor
- 768 KB cache (separate I/D)
- 8192-entry TLB
- CIO bus for I/O
- Maximum RAM of 512 MB
HP 9000/870 Panther (also HP 9000/870S):
- First (SMP) multiprocessor PA-RISC system
- Up to four 50 MHz PCX processors
- 870/100 was uni-processor, 870/200 dual, 870/300 tri and 870/400 quad
- 1024 KB cache (separate I/D)
- 8192-entry TLB
- CIO bus for I/O
- Performance of about 50 MIPS (single-CPU), 90 MIPS (dual-CPU)
- Maximum RAM of 1024 MB with two memory controllers (MC0, MC1) in 16 slots (16�64 MB) [it could be the 1024 MB were only supported on the HP 3000 equivalents]
- Price of about US $440,000 for 870/300, $530,000 for 870/400
822, 832, 842 and 852: Low-Cost NS-2 and PCX
Shortly after, in 1989, lower-end and more compact servers were introduced, apparently also based on the NS-2 and PCX processors but already using the HP-PB I/O bus:7
HP 9000/822 SilverFox Low:
- 25 MHz NS-2 processor
- 32 KB cache (separate I/D)
- 4096-entry TLB
- Maximum RAM of 128 MB (some sources say 64 MB)
- Performance of about 10 MIPS
- Price of about US $20,000 at time of introduction
HP 9000/832 SilverFox High:
- 30 MHz NS-2 processor
- 128 KB cache (separate I/D)
- 4096-entry TLB
- Maximum RAM of 128 MB (some sources say 64 MB)
- Performance of about 15 MIPS
- Price of about US $30,000 at time of introduction
HP 9000/842 SilverBullet Low:
- 32 MHz PCX processor
- 1024 KB cache (separate I/D)
- 8192-entry TLB
- Performance of about 30 MIPS
HP 9000/852 SilverBullet High:
- 50 MHz PCX processor
- 1024 KB cache (separate I/D)
- 8192-entry TLB
- Performance of about 50 MIPS
These 8x2 servers were described as all having CMOS PCX processors in previous versions of this page. This is apparently not correct, as the 822/832 HP brochures state that these systems had NMOS CPUs, with the system block diagrams pointing to a NS-2. The picture for these systems is not really clear, with available benchmark results pointing in an even different direction.
Benchmarks
Assorted MIPS benchmark
numbers for systems with known, unambigious results, in ascending order.
| Model | MIPS |
|---|---|
| 840 | 4.5 |
| 825 | 9 |
| 822 | 10 |
| 850 | 14 |
| 835 | 14 |
| 832 | 15 |
| 845 | 22 |
| 855 | 22 |
| 842 | 30 |
| 852 | 50 |
| 870/100 single |
50 |
| 870/200 dual |
90 |
References
- INFORMATION ON HP9000 SERVERS AND WORKSTATIONS Hewlett Packard Company (1999. Accessed January 2007) and The HP 3000/HP 9000 model spreadsheet (Excel spreadsheet) Allegro Consultants (2004. Accessed January 2007) ↑
- Wayne E. Holt (ed.), Beyond RISC! An Essential Guide to Hewlett-Packard Precision Architecture, p. 95-102. (January 1988: Software Research Northwest Inc.) and Hardware Design of the First HP Precision Architecture Computers (PDF) David A. Fotland et al (March 1987: Hewlett-Packard Journal) ↑
- HP 3000 Series 950 and HP 9000 Model 850S Family CE Handbook (PDF) Hewlett-Packard Company (October 1990. Accessed January 2008 at hpmuseum.net) and HP 9000 Series 800 Model 825S Hardware Technical Data (PDF) Hewlett-Packard Company (September 1988. Accessed January 2008 at hpmuseum.net) and HP 3000/925 and HP 9000/825/835 Computer Systems CE Handbook (PDF) Hewlett-Packard Company (May 1988. Accessed January 2008 at hpmuseum.net) and New midrange members of the Hewlett-Packard Precision Architecture Computer Family Thomas O. Meyer et al (June 1989: Hewlett Packard Journal. Accessed January 2008 at findarticles.com) ↑
- Wayne E. Holt, Beyond RISC! ↑
- Hewlett-Packard Company, HP 3000 Series 950 and HP 9000 Model 850S Family CE Handbook ↑
- Ibid. ↑
- HP 9000 Series 800 Model 822S/832S Technical Data (PDF) Hewlett-Packard Company (1989. Accessed January 2008 at hpmuseum.net) ↑
- For HP 9000/840: Interview with David Fotland, September/October 2008