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Inventing Itanium: How HP Labs helped
create the next-generation chip architecture
June 2001
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When HP rolls out its first computer systems
based on the Itanium processor architecture later this month, it'll
launch a whole new chapter in high-end computing.�But for some
HP scientists, the product launch -- a workstation and two servers
-- marks the culmination of research that began more than a decade
ago.
The Intel Itanium processor is
the first generation of the latest processor architecture co-invented by
Hewlett-Packard and Intel and produced by Intel. These processors are intended
for dynamic Internet-based interactions, complex computations, rich media processing and object- oriented
environments.
The Itanium architecture has its roots in
research that began in�the 1980s, when HP Labs set out to
define an architecture that would converge HP's current lines of
computer system products. This�resulted in what became known as
the PA-RISC architecture (Reduced Instruction Set Computing).
Recognizing that RISC-based architecture would reach its limits,
HP Labs began a research program in Instruction Level Parallelism
(ILP) in early 1989, with the goal of evolving the Very Long
Instruction Word (VLIW) style of architecture to be more applicable
to general-purpose workloads. This research program, which continued
through 1996, yielded the EPIC style of architecture and the
compiler technology for it.
At about the same time the
ILP work began, HP Labs started a separate program to build
an EPIC architecture to replace PA-RISC. What emerged by 1993 was
the PA-WideWord architecture -- the basis of the HP-Intel
alliance and the Itanium processor specification (formerly known as
IA-64).
Itanium�was developed as an extremely
parallel high-performance architecture, carrying out more
instructions in one clock than its architectural predecessors. It
does this by passing the burden of instruction scheduling to the
compiler software that reorders the code for maximum parallelism
while the hardware focuses on executing the instructions issued to
it.
Read about some of the�scientists who contributed to this effort, the
technical reports behind the research or go to the HP Itanium Web site.
Scientists
Bill Worley -
one of the principal architects of PA-RISC and PA-Wide Word
Profile (2001)
Bill Worley interview�(1997)
Rajiv Gupta - headed the joint architecture
team
Profile
(2001)
Rajiv Gupta interview (1999)
Jerry Huck - lead architect, Itanium
processor�specification
Profile
(2001)
Bob Rau - VLIW
pioneer who helped create the EPIC�style of architecture (bio)
Mike Schlansker - lead research on EPIC, a
principal architect of PA-Wide Word (bio)
Vinod Kathail - lead research on EPIC,
architect of EPIC compiler prototype (bio)
Dick
Lampman,�now�Vice President,
Research, Hewlett-Packard and Director,
HP Labs, managed the PA-Wide Word project. (bio)
Technical
Reports
ILP Overviews
Instruction-Level
Parallel Processing�(1992)
Instruction-Level
Parallel Processing: History, Overview and Perspective
(1992)
PA-RISC
The
Hewlett-Packard PA-RISC 8500 Processor (1998)
EPIC Architecture Research�
EPIC:
An Architecture for Instruction-Level Parallelism
Processors�(1999)
Achieving
High Levels of Instruction-Level Parallism with Reduced Hardware
Complexity (1996)
HPL-PD
Architecture Specification: Version 1.1�(1993)
HPL
Play-Doh Architecture Specification�Version
1.0�(1993)
EPIC Compiler Research
Listing below represents only most recent reports -
for earlier reports on this subject, see www.hpl.hp.com/techreports/index.html.)
Efficient
Backtracking Instruction Schedulers (2000)
Control
CPR: A Branch Height Reduction Organization for EPIC Architectures
(1999)
Elcor's
Machine Description System: Version 3.0 (1998)
Machine-Description
Driven Compilers for EPIC Processors (1998)
Meld
scheduling: A Technique for Relaxing Scheduling Complaints
(1997)
Analysis
of Predicted Code (1996)
Profile-Driven
Instruction Level Parallel Scheduling (1996)
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