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Chip Select (NSS) in SPI transfers #10

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@epninety

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@epninety

Trying to send multiple bytes in an SPI transfer from buck50.py, I'm unable to find a method to keep /CS (NSS) asserted for the complete transfer. Presently /CS rises briefly after each byte is sent, which spi devices read as completion of the transfer.

e.g. I enter 'spi' to get to spi mode, then '12 34 56' to send three bytes of data.
On the scope, I see /CS rise for ~2uSec between bytes.

Have I missed a trick in the documentation, is there a way to hold /CS low for the complete transfer?

Current settings
mode : master
xmit-only : disabled
snoop : disabled
select : hardware
baud : 281.25KHz
endian : msb
idle : low
phase : 1st
miso : open-drain
pull : up
speed : 2MHz
nss : active
tx-data : 00
rate : unlimited
busy-wait : 1ms
rx-wait : 1ms
nss-time : 100μs(error:+1.35525e-08ps)
ascii-num : numeric
end : END

(Hardware is a custom board with a genuine STM32 fitted.)

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