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Hi, did you find the solution. I met a issue similar to yours. I can't read mcycle as well as mhpmcount. |
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I wasn't able to find out a way to run that assembly command, no. To read the true hart ID of a core, which was my reason for running that assembly command I made a workaround that stored the hart ID as a "hardcoded" register in my RoCC module. (by "hardcoded" I mean that during the stage when the Chisel is converted into Firrtl [not sure what the correct term is - Elaboration maybe? Compilation?] I assign a Scala variable to the module, which is then turned into a hardware register. Something along these lines (I copied over what's necessary from my module to get the point across; I don't think this will actually compile & run if you take the code ver batim) class MyModule(val enableHartIdCommand: Boolean)(implicit p: Parameters) extends LazyRoCC (opcodes) {
// This is overridden in CanHaveMyModule. 99.U is a placeholder because then it'd be obvious if it's not set properly.
// The value is for the doGetHartid instruction, in the case where Firesim's CPU ids differ from the hart ids.
var hartId = 99.U;
class Impl extends LazyRoCCModuleImp(this) {
// (Skipping a bunch of other code, e.g. other doX/doY instruction variants)
val doGetHartId = io.cmd.bits.inst.funct(4) === true.B
when (doGetHartId) {
// This bit is simplified; in my actual module I have a state machine and
// instead of directly setting io.resp.valid, it goes to the "respond" state
// The important part is the := hartId; when turned to firrtl it becomes "hardcoded"
io.resp.bits.data := hartId
io.resp.valid := true.B
}
}
}
// this trait is added in DigitalTop.scala
trait CanHaveMyModule {
this: HasTiles =>
val mqs = tiles.flatMap { t =>
t match {
case r: RocketTile =>
r.roccs.collect { case mq: MyModule =>
if (mq.enableHartIdCommand) mq.hartId = t.hartId.U
t.hartId -> mq
}
case b: BoomTile =>
b.roccs.collect { case mq: MyModule =>
if (mq.enableHartIdCommand) mq.hartId = t.hartId.U
t.hartId -> mq
}
}
}.toMap
}
class WithMyModule(enableHartIdCommand: Boolean = false) extends Config((site, here, up) => { case BuildRoCC =>
up(BuildRoCC) ++
Seq((p: Parameters) => {
val myModule = LazyModule(new MyModule(enableHartIdCommand)(p))
myModule
})
})(The reason I set enableHartIdCommand to a parameter is because if it's enabled, then Firrtl can't dedupe the verilog for each instance of my module, since the code is different. So I only enable it when i'm building for firesim.) Unfortunately, I don't know how to read mcycle or mhpmcount, sorry. |
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ah, I see. I was thinking cssr instruction is a privileged instruction which might restrict us from using it in a user space. I don't know. I do see some guy use this instruction in a c++ program, like this one https://github.com/ccelio/riscv-hpmcounters. |
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Hi,
These two lines work effectively to identify the current processor ID when running a Verilator simulation:
but when I am running Fedora on firesim (still on a Rocket core, though), and then I attempt to run the same lines, I get an error
Illegal instruction (core dumped). Is that instruction only allowed when doing a bare metal simulation in Verilator/VCS?Here's the hello world:
And here's the output:
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