VHDL projects for combinational and sequential logic design on FPGA.
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Dec 18, 2024 - VHDL
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latches
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Implemented some functionalities for the existing DBMS.
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Jul 19, 2021 - C++
Digital Design laboratory project exploring sequential logic circuits, including latches and flip-flops (RS, D, JK, T, Master-Slave), with interactive NI Multisim simulations and detailed documentation (Logic Design, UNIWA).
counter academic-project digital-design sequential-logic multisim logic-circuits flip-flops latches uniwa nand-gates memory-elements
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Feb 12, 2026
🚦 Digital logic implementation of a 4-way intersection traffic light controller using D-flip flops and state machine design. Features timing-based transitions, safe traffic flow management, and complete cycle control for North-South/East-West directions.
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May 26, 2025
VHDL project for implementing sequential circuits (latches, flip-flops, registers, counters, shift registers) with testbench-based verification in ModelSim (Digital Circuit Design, UNIWA).
simulation vhdl counters academic-project hdl modelsim testbench registers sequential-circuits digital-circuit-design flip-flops latches shift-registers uniwa
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Jan 14, 2026 - VHDL
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