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Multimedia-Processing / Digital-Logic-Design

Star 18

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

fpga digital vhdl verilog learn xilinx digital-logic systemverilog hdl verilog-hdl xilinx-fpga xilinx-vivado digital-logic-design altera-fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 altera-quartus soc-kit altera-cyclone vhdl-verilog
  • Updated Oct 25, 2023
  • Verilog

Amey-Thakur / DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB

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Star 11

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] | SE Semester III | Computer Engineering

computer-science engineering vhdl computer-engineering textbooks digital-systems study-materials digital-logic-design academic-resources university-of-mumbai digital-system-design digital-systems-design digital-logic-design-lab ameythakur amey megasatish reference-books
  • Updated Feb 11, 2026

ramiomer94 / VLSI-design-projects

Star 7

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools
  • Updated Jul 12, 2025
  • Verilog

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