constrained-random-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

A dynamic verification library for Chisel.

my UVM training projects

Custom 16-bit 3-stage pipelined CPU in SystemVerilog with UVM verification, RAW hazard handling, assertions, constrained-random testing, and functional coverage.

SystemVerilog/UVM UART loopback verification with constrained-random sequences, a transaction scoreboard, and functional coverage.

RV32I RISC-V core written in SystemVerilog, with an emphasis on coverage-driven verification using constrained-random stimulus, SVA assertions, and functional coverage

SystemVerilog layered testbench for ALU functional verification — constrained-random, coverage-driven, self-checking scoreboard.

A structured collection of SystemVerilog constraint randomization problems and solutions. Organized by difficulty levels theoretical easy medium and hard coding to support progressive learning. Designed for mastering constraint techniques building reusable SV UVM examples and preparing for Design Verification interviews.

Phase-2 Cycle-3: Verification Fundamentals

End-to-end UART TX/RX verification using SystemVerilog OOP, constrained-random stimulus, functional coverage, SVA assertions, mailboxes, monitors, drivers, and self-checking scoreboards.

AMBA AHB-Lite Memory Verification using SystemVerilog — constrained-random verification, functional coverage, SVA assertions, scoreboard, monitor, driver, and all 8 AHB burst types.

SystemVerilog/UVM verification of a three-channel YAPP packet router: reusable agents, constrained-random traffic, HBUS sequences, and queue-based scoreboarding.

SystemVerilog implementation of AES-128 encryption and decryption , designed for resource efficiency

UVM-based functional verification environment for a 1x3 packet router using SystemVerilog — includes driver, monitor, scoreboard, sequences, and coverage.

Class-based SystemVerilog verification environment for an APB slave, featuring constrained-random testing, mailbox-based communication, scoreboard checking, and SystemVerilog Assertions (SVA).