kendryte_k210: Fix CPU1 ISA configuration to match CPU2#848
Open
no1wudi wants to merge 1 commit intorenode:masterfrom
Open
kendryte_k210: Fix CPU1 ISA configuration to match CPU2#848no1wudi wants to merge 1 commit intorenode:masterfrom
no1wudi wants to merge 1 commit intorenode:masterfrom
Conversation
Align CPU1 with standard rv64imafdc_zicsr_zifencei instead of rv64imacfd_zicsr_zifencei for consistent RISC-V extension ordering.
6f4ec4e to
d66b0c2
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Related issue
N/A - Internal configuration consistency fix
Description
This PR is a style fix that corrects the RISC-V ISA configuration inconsistency in the Kendryte K210 platform.
Usage example
N/A
Additional information