Apply SX1262 register 0x8B5 patch for improved GC1109 RX sensitivity

weebl2000 · weebl2000 · commit a6cb9e0fccb2 · 2026-02-11T02:59:34.000+01:00
Sets the LSB of undocumented SX1262 register 0x8B5 on Heltec V4 and Wireless Tracker V2 boards with the GC1109 FEM. This patch was recommended by Heltec/Semtech and tested in MeshCore PR #1398, where it significantly reduced packet loss on the Heltec V4.
diff --git a/src/mesh/SX126xInterface.cpp b/src/mesh/SX126xInterface.cpp
@@ -171,6 +171,19 @@ template <typename T> bool SX126xInterface<T>::init()
         LOG_INFO("Set RX gain to power saving mode (boosted mode off); result: %d", result);
     }
 
+#ifdef USE_GC1109_PA
+    // Undocumented SX1262 register patch recommended by Heltec/Semtech for improved RX sensitivity
+    // on boards with the GC1109 FEM. Sets LSB of register 0x8B5.
+    // Reference: https://github.com/meshcore-dev/MeshCore/pull/1398
+    {
+        uint8_t regVal = 0;
+        lora.readRegister(0x8B5, &regVal, 1);
+        regVal |= 0x01;
+        lora.writeRegister(0x8B5, &regVal, 1);
+        LOG_INFO("Applied SX1262 register 0x8B5 patch for GC1109 RX improvement");
+    }
+#endif
+
 #if 0
     // Read/write a register we are not using (only used for FSK mode) to test SPI comms
     uint8_t crcLSB = 0;
