Discussions

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  A new Version V4.1.0

  BFH-ktt1 announced Feb 15, 2026 in Announcements

  

  

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  Digital Accessibility Information

  YSUCTS asked Jan 7, 2026 in Q&A · Answered

  

  

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  Preloading several RAM memories when executing circuits from command line

  LAPSyLAB started Dec 7, 2025 in General

  

  

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  logisim-evolution can be run on the Android platform.(3.8.0)

  oldcwj started Sep 25, 2024 in General

  

  

  

  

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  A new Version 4.0.0

  BFH-ktt1 announced Sep 7, 2025 in Announcements

  

  

  

  

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  Loading Logisim memory - Logisim hex

  documentation What's up Doc?

  frogandspanner asked Aug 12, 2025 in Q&A · Answered

  

  

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  logisim in the browser?

  enhancement help wanted pri -1 Not that crucial (lower priority)

  regehr started Dec 20, 2023 in General

  

  

  

  

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  Will there be support for adding Verilog modules instead of VHDL entities?

  thejonmonte started Aug 7, 2021 in General

  

  

  

  

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  Pong game with score

  zdimension started May 1, 2025 in Show and tell

  

  

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  Simple static web server using the Telnet component

  zdimension started May 1, 2025 in Show and tell

  

  

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  Erroneus behaviour while using buffers

  lUNuXl asked Apr 14, 2025 in Q&A · Answered

  

  

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  How do I use port i/o and reaper bus ?

  documentation What's up Doc?

  Negan795 asked Mar 29, 2025 in Q&A · Answered

  

  

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  Select Vivado's software & Xilinx vivado toolpath

  vicvicvarumg started Mar 8, 2025 in General

  

  

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  Add Efinix

  168-fan asked Jan 16, 2025 in Q&A · Answered

  

  

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  Logisim Evolution Commands

  Y2605 asked Jan 2, 2025 in Q&A · Answered

  

  

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  can't unistall logisim evolution

  pityka3000 asked Dec 15, 2024 in Q&A · Answered

  

  

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  Verilog/VHDL programmer needed for contribution

  ITSMijaiL started Oct 11, 2024 in Dev talk

  

  

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  After a long time a new version of Logisim: V3.9.0

  BFH-ktt1 announced Aug 15, 2024 in Announcements

  

  

  

  

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  Feature Request: TTL 74173

  enhancement help wanted

  lshkim started Sep 6, 2024 in Ideas

  

  

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  Clock frequency counter/output

  Igordh started Aug 18, 2024 in Ideas

  

  

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  Is there any way to better display/visualize binary values of busses, registers, ... ?

  LAPSyLAB started May 17, 2023 in General

  

  

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  Logisim-evolution internal architecture..

  efecollie asked Jan 8, 2023 in Q&A · Answered

  

  

  

  

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  Much better minterm optimizier

  gh228df started Jun 22, 2024 in General

  

  

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  Why doesn't L.E support verilog?

  Slicudis asked Jul 25, 2024 in Q&A · Answered

  

  

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  How do I convert floating (undefined) states to "low" but still maintaining compatibility with FPGAs?

  Slicudis asked May 30, 2024 in Q&A · Unanswered

  

  

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