Fourth-year Electrical & Electronic Engineering undergraduate at Yonsei University, Seoul.
I build hardware for machine learning — and, increasingly, for the part of machine learning that is actually slow: moving data. My capstone started as an accelerator project and ended up as a memory-system project, which is roughly the arc I want to keep following.
Current interest: memory-centric computing — processing near memory, accelerator microarchitecture, and the gap between what a datapath can compute and what the memory system can feed it.
The capstone is written up as a paper: A Near-Data Processing Approach to Accelerating Compaction in LSM-tree Key-Value Stores (with Jaesik Jang).
| Project | What it is | Result |
|---|---|---|
| gem5-pnm-lsm-compaction | A processing-near-memory unit in the DIMM buffer chip that takes over RocksDB compaction. Modified gem5 (full-system) plus a RocksDB fork, coupled by an MMIO contract. | Write throughput +45–59%, CPU L2 misses −54 to −64%, across two full-system runs |
| systolic-mlp-accelerator-zynq | 16×16 output-stationary systolic array for int8 MLP inference on Zynq-7020, with matrix tiling to keep the working set in on-chip memory. | Timing met at 100 MHz; in simulation the RTL's output matches the NumPy reference on all 16 clips |
| npu-conv-accelerator-pynq | Configurable convolution accelerator in SystemVerilog on PYNQ-Z2 — AXI4-Lite CSRs, BRAM tiling, and a Python golden model to check it against. | RTL matches the golden model; timing met at 50 MHz in 12% of the LUTs |
| fpga-cnn-accelerator-labs | Verilog fundamentals through UART, custom AXI IP, Sobel filtering, and an MNIST CNN accelerator on Spartan-7 / Zynq-7000. | All 17 testbenches run from a clone; the CNN core is pipelined to meet timing at 100 MHz |
| tinygpt-transformer-from-scratch | A bigram-to-GPT course curriculum in PyTorch, documented stage by stage, with my own TinyGPT trained on a new dataset at the end. | Held-out loss 1.36 at its best epoch, on a contiguous split; one script checks every notebook's losses against the README table |
The last one is deliberate. If you are designing silicon for a workload, you should be able to write the workload.
Verilog / SystemVerilog · Vivado · gem5 · C / C++ · Python / PyTorch · Zynq-7000, Spartan-7
Seoul, Korea · [email protected]