Reusable Verilog cores focused on cryptography, DSP, and neural acceleration

A growing collection of reusable, parameterized hardware cores for learning, prototyping, and integration into advanced digital design projects. Our primary focus is on cryptographic cores, DSP cores, neural accelerators, and other high‑performance building blocks for modern systems.

Whether you’re a beginner exploring Verilog or an experienced designer, your contributions are welcome!

This repository contains multiple independent, reusable Verilog hardware cores. Each core can be explored, simulated, and integrated individually using standard HDL tools.

This section provides general guidance to help new users get started quickly. Core-specific instructions may vary and are typically documented within the respective core directories.

• A Verilog simulator (e.g., Icarus Verilog, Verilator, or a compatible simulator)
• GTKWave or a compatible waveform viewer (optional, for signal inspection)

1. Navigate to the directory of the desired hardware core.
2. Compile the Verilog source files along with the corresponding testbench.
3. Run the simulation using your chosen simulator.
4. Inspect simulation logs or waveforms to verify correct functionality.

We focus on building powerful hardware cores that can serve as reusable building blocks.
Here’s a snapshot of what we have right now and what we might consider building later:

• ChaCha20 stream cipher ➡️
• AES block cipher ➡️
• PRNGs — Multiple modules including PCG64-DXSM, SplitMix64, philox-4*32-10, and 5 other PRNG variants ➡️
• SHA‑1 / SHA‑256 hash cores
• RSA / ECC accelerators
• Grain‑128 / Grain‑128a

• FIR, IIR filter modules
• FFT (Fast Fourier Transform) prototype
• Convolution engines for signal/image processing

• Basic matrix multiplication core
• Convolutional layer accelerators
• Activation function modules (ReLU, Sigmoid, Tanh)
• RNN/LSTM building blocks
• Quantized neural network primitives

Read the contribution guide here:
👉 Contribution Guidelines

If you run into any issues or want help contributing, feel free to open a Discussion:
👉 Discussions

• Icarus Verilog — Simulation
• Verilator — Linting & static checks
• GTKWave — Waveform viewing
• EDA Playground — Quick online testing

• Lattice iCE40 UP5K
• Xilinx Artix-7 XC7A35T

If you use this work in your research, please cite it using the Zenodo DOI:

@misc{OpenSiliconHub_ChaCha20_2025,
  author       = {Abhilash M},
  title        = {OpenSiliconHub: ChaCha20 Hardware Core},
  year         = {2025},
  publisher    = {Zenodo},
  doi          = {10.5281/zenodo.17895634},
  url          = {https://doi.org/10.5281/zenodo.17895634}
}

For module requests, ideas, improvements, or collaboration, use the GitHub Discussions section of the repository.

This project is licensed under the MIT License — see LICENSE for details.