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3249 lines (2839 loc) · 110 KB
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/*-------------------------------------------------------------------------
*
* MPLAB-C30 dsPIC30F4011 processor header
*
* (c) Copyright 2005-2006 Microchip Technology, All rights reserved
*
* File Description / Notes:
* =========================
* 1] This header file defines special function registers (SFR), and useful
* macros for the dsPIC30Fxxxx Family of Digital Signal
* Controllers (also referred to as the dsPIC).
* 2] The register and bit names used in this file match the
* dsPIC30Fxxxx data sheets as closely as possible.
* 3] The memory locations of the registers defined in this header file are
* specified in the respective linker scripts.
* 4] SFR definitions are listed in the ascending order of memory addresses
* and are grouped based on the module they belong to. For e.g., WREG10
* is listed before ACCAL, and the Core SFRs are grouped separately
* from the Interrupt Controller SFRs or the General Purpose Timer SFRs.
*
* Revision History:
* =================
* --------------------------------------------------------------------------
* Rev: Date: Details: Who:
* --------------------------------------------------------------------------
* 2.0 23 Apr 2003 New file P Sinha
* 2.0a 24 Apr 2003 Added CEID bit P Sinha
* 2.0b 30 Apr 2003 Removed suffix 'B' from device number P Sinha
* 2.0c 2 May 2003 'H' suffix added to CiRXFnEID/CiRXMnEID P Sinha
* 2.1 2 Jun 2003 Relocated CANCAP bit to CxCTRL P Sinha
* 2.2 17 Jun 2003 Renamed CONV bit to DONE P Sinha
* 2.3 20 Jun 2003 Corrections in Config Fuses comments P Sinha
* 2.3a 23 Jun 2003 Typos in CAN structure corrected P Sinha
* 2.3b 5 Aug 2003 Added TUN1-4 bits in OSCCON P Sinha
* 2.3c 18 Sep 2003 DFLTCON changes P Sinha
* 2.4 10 Oct 2003 Added macros for data allocation and ISRs P Sinha
* 2.5 25 Nov 2003 Renamed TUN1-4 bits to TUNF0-3 P Sinha
* 3.0 30 Mar 2004 Added defines for unique SFR bit names P Sinha
* 3.1 5 Apr 2004 Added underscore before SFR bit labels P Sinha
* 3.1a 8 Apr 2004 Added config macros for FRC w/ PLL modes P Sinha
* 3.2 11 Apr 2004 Enhanced config macro usage examples P Sinha
* 3.3 14 Apr 2004 Corrected a typo in the _U1RXIE bit label P Sinha
* 4.0 28 Sep 2004 Changed data allocation macro definitions P Sinha
* 4.1 22 Dec 2004 Corrected a typo in the _U1RXIE definition P Sinha
* 4.1a 14 Mar 2005 Removed LVD definitions P Sinha
* 4.2 4 Apr 2005 Renamed EC_IO to ECIO and ERC_IO to ERCIO P Sinha
* 4.2a 27 Jun 2005 Fixed typos in comments regarding macros G McCar
* 4.3 1 Jul 2005 Updated section syntax in config macros P Sinha
* v3.00 02 Feb 2007 Added processor check S Curtis
* (Rev reflects compiler version)
* --------------------------------------------------------------------------
*
* ------------------------------------------------------------------------*/
#ifndef __dsPIC30F4011__
#error "Include file does not match processor setting"
#endif
#ifndef __30F4011_H
#define __30F4011_H
/* ------------------------- */
/* Core Register Definitions */
/* ------------------------- */
/* W registers W0-W15 */
extern volatile unsigned int WREG0 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG1 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG2 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG3 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG4 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG5 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG6 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG7 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG8 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG9 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG10 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG11 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG12 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG13 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG14 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG15 __attribute__((__sfr__,__deprecated__,__unsafe__));
/* SPLIM: Stack Pointer Limit */
extern volatile unsigned int SPLIM __attribute__((__sfr__));
/* Alternative access structure for the 40-bit accumulators */
typedef struct tagACC {
unsigned int L;
unsigned int H;
unsigned char U;
} ACC;
/* Acc A<15:0> */
extern volatile unsigned int ACCAL __attribute__((__sfr__));
/* Acc A<31:16> */
extern volatile unsigned int ACCAH __attribute__((__sfr__));
/* Acc A<39:32> */
extern volatile unsigned char ACCAU __attribute__((__sfr__));
/* Acc A defined as a structure consisting of the 3 parts */
extern volatile ACC ACCA __attribute__((__sfr__));
/* Acc B<15:0> */
extern volatile unsigned int ACCBL __attribute__((__sfr__));
/* Acc B<31:16> */
extern volatile unsigned int ACCBH __attribute__((__sfr__));
/* Acc B<39:32> */
extern volatile unsigned char ACCBU __attribute__((__sfr__));
/* Acc B defined as a structure consisting of the 3 parts */
extern volatile ACC ACCB __attribute__((__sfr__));
/* PCL: Program Counter low word */
extern volatile unsigned int PCL __attribute__((__sfr__));
/* PCH: Program Counter high byte */
extern volatile unsigned char PCH __attribute__((__sfr__));
/* TBLPAG: Table Page Register */
extern volatile unsigned char TBLPAG __attribute__((__sfr__));
/* PSVPAG: Program Space Visibility Page Register */
extern volatile unsigned char PSVPAG __attribute__((__sfr__));
/* RCOUNT: REPEAT loop count */
extern volatile unsigned int RCOUNT __attribute__((__sfr__));
/* DCOUNT: DO loop count */
extern volatile unsigned int DCOUNT __attribute__((__sfr__));
/* DOSTARTL: DO loop start address bits <15:0> */
extern volatile unsigned int DOSTARTL __attribute__((__sfr__));
/* DOSTARTH: DO loop start address bits <23:16> */
extern volatile unsigned int DOSTARTH __attribute__((__sfr__));
/* DOENDL: DO loop end address bits <15:0> */
extern volatile unsigned int DOENDL __attribute__((__sfr__));
/* DOENDH: DO loop end address bits <23:16> */
extern volatile unsigned int DOENDH __attribute__((__sfr__));
/* SR: Status Register */
extern volatile unsigned int SR __attribute__((__sfr__));
typedef struct tagSRBITS {
unsigned C :1; /* Carry flag */
unsigned Z :1; /* Sticky Zero flag */
unsigned OV :1; /* Overflow flag */
unsigned N :1; /* Negative flag */
unsigned RA :1; /* REPEAT loop active flag */
unsigned IPL :3; /* CPU Interrupt Priority Level */
unsigned DC :1; /* Digit Carry flag */
unsigned DA :1; /* DO loop active flag */
unsigned SAB :1; /* Combined A/B saturation flag */
unsigned OAB :1; /* Combined A/B overflow flag */
unsigned SB :1; /* Acc B saturation flag */
unsigned SA :1; /* Acc A saturation flag */
unsigned OB :1; /* Acc B overflow flag */
unsigned OA :1; /* Acc A overflow flag */
} SRBITS;
extern volatile SRBITS SRbits __attribute__((__sfr__));
/* CORCON: CPU Mode control Register */
extern volatile unsigned int CORCON __attribute__((__sfr__));
typedef struct tagCORCONBITS {
unsigned IF :1; /* Integer/Fractional mode */
unsigned RND :1; /* Rounding mode */
unsigned PSV :1; /* Program Space Visibility enable */
unsigned IPL3 :1; /* CPU Interrupt Priority Level bit 3 */
unsigned ACCSAT :1; /* Acc saturation mode */
unsigned SATDW :1; /* Data space write saturation enable */
unsigned SATB :1; /* Acc B saturation enable */
unsigned SATA :1; /* Acc A saturation enable */
unsigned DL :3; /* DO loop nesting level status */
unsigned EDT :1; /* Early DO loop termination control */
unsigned US :1; /* Signed/Unsigned mode */
unsigned :3;
} CORCONBITS;
extern volatile CORCONBITS CORCONbits __attribute__((__sfr__));
/* MODCON: Modulo Addressing Control Register */
extern volatile unsigned int MODCON __attribute__((__sfr__));
typedef struct tagMODCONBITS {
unsigned XWM :4; /* X-RAGU/X-WAGU modulo addressing register select */
unsigned YWM :4; /* Y-RAGU modulo addressing register select */
unsigned BWM :4; /* Bit-reversed addressing register select */
unsigned :2;
unsigned YMODEN :1; /* Y-RAGU modulo addressing enable */
unsigned XMODEN :1; /* X-RAGU/X-WAGU modulo addressing enable */
} MODCONBITS;
extern volatile MODCONBITS MODCONbits __attribute__((__sfr__));
/* XMODSRT: X-RAGU/X-WAGU modulo buffer start address */
extern volatile unsigned int XMODSRT __attribute__((__sfr__));
/* XMODEND: X-RAGU/X-WAGU modulo buffer end address */
extern volatile unsigned int XMODEND __attribute__((__sfr__));
/* YMODSRT: Y-RAGU modulo buffer start address */
extern volatile unsigned int YMODSRT __attribute__((__sfr__));
/* YMODEND: Y-RAGU modulo buffer end address */
extern volatile unsigned int YMODEND __attribute__((__sfr__));
/* XBREV: X-WAGU Bit-reversed Addressing Control Register */
extern volatile unsigned int XBREV __attribute__((__sfr__));
typedef struct tagXBREVBITS {
unsigned XB :15; /* Bit-reversed addressing register select */
unsigned BREN :1; /* Bit-reversed addressing enable */
} XBREVBITS;
extern volatile XBREVBITS XBREVbits __attribute__((__sfr__));
/* DISICNT: Disable Interrupt Cycle Count */
extern volatile unsigned int DISICNT __attribute__((__sfr__));
typedef struct tagDISICNTBITS {
unsigned DISICNT:14;
unsigned :2;
} DISICNTBITS;
extern volatile DISICNTBITS DISICNTbits __attribute__((__sfr__));
/* ----------------------------------------- */
/* Interrupt Controller register definitions */
/* ----------------------------------------- */
/* INTCON1: Interrupt Control Register 1 */
extern volatile unsigned int INTCON1 __attribute__((__sfr__));
typedef struct tagINTCON1BITS {
unsigned :1;
unsigned OSCFAIL:1;
unsigned STKERR :1;
unsigned ADDRERR:1;
unsigned MATHERR:1;
unsigned :3;
unsigned COVTE :1;
unsigned OVBTE :1;
unsigned OVATE :1;
unsigned :4;
unsigned NSTDIS :1;
} INTCON1BITS;
extern volatile INTCON1BITS INTCON1bits __attribute__((__sfr__));
/* INTCON2: Interrupt Control Register 2 */
extern volatile unsigned int INTCON2 __attribute__((__sfr__));
typedef struct tagINTCON2BITS {
unsigned INT0EP :1;
unsigned INT1EP :1;
unsigned INT2EP :1;
unsigned :11;
unsigned DISI :1;
unsigned ALTIVT :1;
} INTCON2BITS;
extern volatile INTCON2BITS INTCON2bits __attribute__((__sfr__));
/* IFS0: Interrupt Flag Status Register 0 */
extern volatile unsigned int IFS0 __attribute__((__sfr__));
typedef struct tagIFS0BITS {
unsigned INT0IF :1;
unsigned IC1IF :1;
unsigned OC1IF :1;
unsigned T1IF :1;
unsigned IC2IF :1;
unsigned OC2IF :1;
unsigned T2IF :1;
unsigned T3IF :1;
unsigned SPI1IF :1;
unsigned U1RXIF :1;
unsigned U1TXIF :1;
unsigned ADIF :1;
unsigned NVMIF :1;
unsigned SI2CIF :1;
unsigned MI2CIF :1;
unsigned CNIF :1;
} IFS0BITS;
extern volatile IFS0BITS IFS0bits __attribute__((__sfr__));
/* IFS1: Interrupt Flag Status Register 1 */
extern volatile unsigned int IFS1 __attribute__((__sfr__));
typedef struct tagIFS1BITS {
unsigned INT1IF :1;
unsigned IC7IF :1;
unsigned IC8IF :1;
unsigned OC3IF :1;
unsigned OC4IF :1;
unsigned T4IF :1;
unsigned T5IF :1;
unsigned INT2IF :1;
unsigned U2RXIF :1;
unsigned U2TXIF :1;
unsigned :1;
unsigned C1IF :1;
unsigned :4;
} IFS1BITS;
extern volatile IFS1BITS IFS1bits __attribute__((__sfr__));
/* IFS2: Interrupt Flag Status Register 2 */
extern volatile unsigned int IFS2 __attribute__((__sfr__));
typedef struct tagIFS2BITS {
unsigned :7;
unsigned PWMIF :1;
unsigned QEIIF :1;
unsigned :2;
unsigned FLTAIF :1;
unsigned :4;
} IFS2BITS;
extern volatile IFS2BITS IFS2bits __attribute__((__sfr__));
/* IEC0: Interrupt Enable Control Register 0 */
extern volatile unsigned int IEC0 __attribute__((__sfr__));
typedef struct tagIEC0BITS {
unsigned INT0IE :1;
unsigned IC1IE :1;
unsigned OC1IE :1;
unsigned T1IE :1;
unsigned IC2IE :1;
unsigned OC2IE :1;
unsigned T2IE :1;
unsigned T3IE :1;
unsigned SPI1IE :1;
unsigned U1RXIE :1;
unsigned U1TXIE :1;
unsigned ADIE :1;
unsigned NVMIE :1;
unsigned SI2CIE :1;
unsigned MI2CIE :1;
unsigned CNIE :1;
} IEC0BITS;
extern volatile IEC0BITS IEC0bits __attribute__((__sfr__));
/* IEC1: Interrupt Enable Control Register 1 */
extern volatile unsigned int IEC1 __attribute__((__sfr__));
typedef struct tagIEC1BITS {
unsigned INT1IE :1;
unsigned IC7IE :1;
unsigned IC8IE :1;
unsigned OC3IE :1;
unsigned OC4IE :1;
unsigned T4IE :1;
unsigned T5IE :1;
unsigned INT2IE :1;
unsigned U2RXIE :1;
unsigned U2TXIE :1;
unsigned :1;
unsigned C1IE :1;
unsigned :4;
} IEC1BITS;
extern volatile IEC1BITS IEC1bits __attribute__((__sfr__));
/* IEC2: Interrupt Enable Control Register 2 */
extern volatile unsigned int IEC2 __attribute__((__sfr__));
typedef struct tagIEC2BITS {
unsigned :7;
unsigned PWMIE :1;
unsigned QEIIE :1;
unsigned :2;
unsigned FLTAIE :1;
unsigned :4;
} IEC2BITS;
extern volatile IEC2BITS IEC2bits __attribute__((__sfr__));
/* IPC0: Interrupt Priority Control Register 0 */
extern volatile unsigned int IPC0 __attribute__((__sfr__));
typedef struct tagIPC0BITS {
unsigned INT0IP :3;
unsigned :1;
unsigned IC1IP :3;
unsigned :1;
unsigned OC1IP :3;
unsigned :1;
unsigned T1IP :3;
unsigned :1;
} IPC0BITS;
extern volatile IPC0BITS IPC0bits __attribute__((__sfr__));
/* IPC1: Interrupt Priority Control Register 1 */
extern volatile unsigned int IPC1 __attribute__((__sfr__));
typedef struct tagIPC1BITS {
unsigned IC2IP :3;
unsigned :1;
unsigned OC2IP :3;
unsigned :1;
unsigned T2IP :3;
unsigned :1;
unsigned T3IP :3;
unsigned :1;
} IPC1BITS;
extern volatile IPC1BITS IPC1bits __attribute__((__sfr__));
/* IPC2: Interrupt Priority Control Register 2 */
extern volatile unsigned int IPC2 __attribute__((__sfr__));
typedef struct tagIPC2BITS {
unsigned SPI1IP :3;
unsigned :1;
unsigned U1RXIP :3;
unsigned :1;
unsigned U1TXIP :3;
unsigned :1;
unsigned ADIP :3;
unsigned :1;
} IPC2BITS;
extern volatile IPC2BITS IPC2bits __attribute__((__sfr__));
/* IPC3: Interrupt Priority Control Register 3 */
extern volatile unsigned int IPC3 __attribute__((__sfr__));
typedef struct tagIPC3BITS {
unsigned NVMIP :3;
unsigned :1;
unsigned SI2CIP :3;
unsigned :1;
unsigned MI2CIP :3;
unsigned :1;
unsigned CNIP :3;
unsigned :1;
} IPC3BITS;
extern volatile IPC3BITS IPC3bits __attribute__((__sfr__));
/* IPC4: Interrupt Priority Control Register 4 */
extern volatile unsigned int IPC4 __attribute__((__sfr__));
typedef struct tagIPC4BITS {
unsigned INT1IP :3;
unsigned :1;
unsigned IC7IP :3;
unsigned :1;
unsigned IC8IP :3;
unsigned :1;
unsigned OC3IP :3;
unsigned :1;
} IPC4BITS;
extern volatile IPC4BITS IPC4bits __attribute__((__sfr__));
/* IPC5: Interrupt Priority Control Register 5 */
extern volatile unsigned int IPC5 __attribute__((__sfr__));
typedef struct tagIPC5BITS {
unsigned OC4IP :3;
unsigned :1;
unsigned T4IP :3;
unsigned :1;
unsigned T5IP :3;
unsigned :1;
unsigned INT2IP :3;
unsigned :1;
} IPC5BITS;
extern volatile IPC5BITS IPC5bits __attribute__((__sfr__));
/* IPC6: Interrupt Priority Control Register 6 */
extern volatile unsigned int IPC6 __attribute__((__sfr__));
typedef struct tagIPC6BITS {
unsigned U2RXIP :3;
unsigned :1;
unsigned U2TXIP :3;
unsigned :5;
unsigned C1IP :3;
unsigned :1;
} IPC6BITS;
extern volatile IPC6BITS IPC6bits __attribute__((__sfr__));
/* IPC9: Interrupt Priority Control Register 9 */
extern volatile unsigned int IPC9 __attribute__((__sfr__));
typedef struct tagIPC9BITS {
unsigned :12;
unsigned PWMIP :3;
unsigned :1;
} IPC9BITS;
extern volatile IPC9BITS IPC9bits __attribute__((__sfr__));
/* IPC10: Interrupt Priority Control Register 10 */
extern volatile unsigned int IPC10 __attribute__((__sfr__));
typedef struct tagIPC10BITS {
unsigned QEIIP :3;
unsigned :9;
unsigned FLTAIP :3;
unsigned :1;
} IPC10BITS;
extern volatile IPC10BITS IPC10bits __attribute__((__sfr__));
/* INTTREG: Interrupt Controller Test Register */
extern volatile unsigned int INTTREG __attribute__((__sfr__));
typedef struct tagINTTREGBITS {
unsigned VECNUM :6;
unsigned :2;
unsigned ILR :4;
unsigned :1;
unsigned VHOLD :1;
unsigned TMODE :1;
unsigned IRQTOCPU:1;
} INTTREGBITS;
extern volatile INTTREGBITS INTTREGbits __attribute__((__sfr__));
/* ---------------------------------------------- */
/* Input Change Notification register definitions */
/* ---------------------------------------------- */
/* CNEN1: Input Change Notification Interrupt Enable Register 1 */
extern volatile unsigned int CNEN1 __attribute__((__sfr__));
typedef struct tagCNEN1BITS {
unsigned CN0IE :1;
unsigned CN1IE :1;
unsigned CN2IE :1;
unsigned CN3IE :1;
unsigned CN4IE :1;
unsigned CN5IE :1;
unsigned CN6IE :1;
unsigned CN7IE :1;
unsigned :8;
} CNEN1BITS;
extern volatile CNEN1BITS CNEN1bits __attribute__((__sfr__));
/* CNEN2: Input Change Notification Interrupt Enable Register 2 */
extern volatile unsigned int CNEN2 __attribute__((__sfr__));
typedef struct tagCNEN2BITS {
unsigned :1;
unsigned CN17IE :1;
unsigned CN18IE :1;
unsigned :13;
} CNEN2BITS;
extern volatile CNEN2BITS CNEN2bits __attribute__((__sfr__));
/* CNPU1: Input Change Notification Pullup Enable Register 1 */
extern volatile unsigned int CNPU1 __attribute__((__sfr__));
typedef struct tagCNPU1BITS {
unsigned CN0PUE :1;
unsigned CN1PUE :1;
unsigned CN2PUE :1;
unsigned CN3PUE :1;
unsigned CN4PUE :1;
unsigned CN5PUE :1;
unsigned CN6PUE :1;
unsigned CN7PUE :1;
unsigned :8;
} CNPU1BITS;
extern volatile CNPU1BITS CNPU1bits __attribute__((__sfr__));
/* CNPU2: Input Change Notification Pullup Enable Register 2 */
extern volatile unsigned int CNPU2 __attribute__((__sfr__));
typedef struct tagCNPU2BITS {
unsigned :1;
unsigned CN17PUE:1;
unsigned CN18PUE:1;
unsigned :13;
} CNPU2BITS;
extern volatile CNPU2BITS CNPU2bits __attribute__((__sfr__));
/* --------------------------- */
/* Timer1 register definitions */
/* --------------------------- */
/* Generic structure for Timer 1 Control Register */
typedef struct tagTCON_16BIT {
unsigned :1;
unsigned TCS :1;
unsigned TSYNC :1;
unsigned :1;
unsigned TCKPS :2;
unsigned TGATE :1;
unsigned :6;
unsigned TSIDL :1;
unsigned :1;
unsigned TON :1;
} TCON_16BIT;
/* TMR1: Timer 1 Count Register */
extern volatile unsigned int TMR1 __attribute__((__sfr__));
/* PR1: Timer 1 Period Register */
extern volatile unsigned int PR1 __attribute__((__sfr__));
/* T1CON: Timer 1 Control Register */
extern volatile unsigned int T1CON __attribute__((__sfr__));
extern volatile TCON_16BIT T1CONbits __attribute__((__sfr__));
/* ----------------------------- */
/* Timer2/3 register definitions */
/* ----------------------------- */
/* Generic structure for Timer 2 and Timer 4 Control Registers */
typedef struct tagTCON_EVEN {
unsigned :1;
unsigned TCS :1;
unsigned :1;
unsigned T32 :1;
unsigned TCKPS :2;
unsigned TGATE :1;
unsigned :6;
unsigned TSIDL :1;
unsigned :1;
unsigned TON :1;
} TCON_EVEN;
/* Generic structure for Timer 3 and Timer 5 Control Registers */
typedef struct tagTCON_ODD {
unsigned :1;
unsigned TCS :1;
unsigned :2;
unsigned TCKPS :2;
unsigned TGATE :1;
unsigned :6;
unsigned TSIDL :1;
unsigned :1;
unsigned TON :1;
} TCON_ODD;
/* TMR2: Timer 2 Count Register */
extern volatile unsigned int TMR2 __attribute__((__sfr__));
/* TMR3HLD: Timer 3 Holding Register */
extern volatile unsigned int TMR3HLD __attribute__((__sfr__));
/* TMR3: Timer 3 Count Register */
extern volatile unsigned int TMR3 __attribute__((__sfr__));
/* PR2: Timer 2 Period Register */
extern volatile unsigned int PR2 __attribute__((__sfr__));
/* PR3: Timer 3 Period Register */
extern volatile unsigned int PR3 __attribute__((__sfr__));
/* T2CON: Timer 2 Control Register */
extern volatile unsigned int T2CON __attribute__((__sfr__));
extern volatile TCON_EVEN T2CONbits __attribute__((__sfr__));
/* T3CON: Timer 3 Control Register */
extern volatile unsigned int T3CON __attribute__((__sfr__));
extern volatile TCON_ODD T3CONbits __attribute__((__sfr__));
/* ----------------------------- */
/* Timer4/5 register definitions */
/* ----------------------------- */
/* TMR4: Timer 4 Count Register */
extern volatile unsigned int TMR4 __attribute__((__sfr__));
/* TMR5HLD: Timer 5 Holding Register */
extern volatile unsigned int TMR5HLD __attribute__((__sfr__));
/* TMR5: Timer 5 Count Register */
extern volatile unsigned int TMR5 __attribute__((__sfr__));
/* PR4: Timer 4 Period Register */
extern volatile unsigned int PR4 __attribute__((__sfr__));
/* PR5: Timer 5 Period Register */
extern volatile unsigned int PR5 __attribute__((__sfr__));
/* T4CON: Timer 4 Control Register */
extern volatile unsigned int T4CON __attribute__((__sfr__));
extern volatile TCON_EVEN T4CONbits __attribute__((__sfr__));
/* T5CON: Timer 5 Control Register */
extern volatile unsigned int T5CON __attribute__((__sfr__));
extern volatile TCON_ODD T5CONbits __attribute__((__sfr__));
/* ------------------------------------------------- */
/* Quadrature Encoder Interface register definitions */
/* ------------------------------------------------- */
/* QEICON: QEI Control Register */
extern volatile unsigned int QEICON __attribute__((__sfr__));
typedef struct tagQEICONBITS {
unsigned UPDN_SRC:1;
unsigned TQCS :1;
unsigned POSRES :1;
unsigned TQCKPS :2;
unsigned TQGATE :1;
unsigned PCDOUT :1;
unsigned SWPAB :1;
unsigned QEIM :3;
unsigned UPDN :1;
unsigned INDX :1;
unsigned QEISIDL:1;
unsigned :1;
unsigned CNTERR :1;
} QEICONBITS;
extern volatile QEICONBITS QEICONbits __attribute__((__sfr__));
/* DFLTCON: Digital Filter Control Register */
extern volatile unsigned int DFLTCON __attribute__((__sfr__));
typedef struct tagDFLTCONBITS {
unsigned :4;
unsigned QECK :3;
unsigned QEOUT :1;
unsigned CEID :1;
unsigned IMV :2;
unsigned :5;
} DFLTCONBITS;
extern volatile DFLTCONBITS DFLTCONbits __attribute__((__sfr__));
/* POSCNT: Position Counter Register */
extern volatile unsigned int POSCNT __attribute__((__sfr__));
/* MAXCNT: Maximum Count Register */
extern volatile unsigned int MAXCNT __attribute__((__sfr__));
/* ---------------------------------- */
/* Input Capture register definitions */
/* ---------------------------------- */
/* Generic structure of entire SFR area for each Input Capture module */
typedef struct tagIC {
unsigned int icxbuf;
unsigned int icxcon;
} IC, *PIC;
/* SFR blocks for each Input Capture module */
extern volatile IC IC1 __attribute__((__sfr__));
extern volatile IC IC2 __attribute__((__sfr__));
extern volatile IC IC7 __attribute__((__sfr__));
extern volatile IC IC8 __attribute__((__sfr__));
/* Generic structure for Input Capture Control Registers */
typedef struct tagICxCONBITS {
unsigned ICM :3;
unsigned ICBNE :1;
unsigned ICOV :1;
unsigned ICI :2;
unsigned ICTMR :1;
unsigned :5;
unsigned ICSIDL :1;
unsigned :2;
} ICxCONBITS;
/* IC1BUF: Input Capture 1 Buffer */
extern volatile unsigned int IC1BUF __attribute__((__sfr__));
/* IC1CON: Input Capture 1 Control Register */
extern volatile unsigned int IC1CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC1CONbits __attribute__((__sfr__));
/* IC2BUF: Input Capture 2 Buffer */
extern volatile unsigned int IC2BUF __attribute__((__sfr__));
/* IC2CON: Input Capture 2 Control Register */
extern volatile unsigned int IC2CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC2CONbits __attribute__((__sfr__));
/* IC7BUF: Input Capture 7 Buffer */
extern volatile unsigned int IC7BUF __attribute__((__sfr__));
/* IC7CON: Input Capture 7 Control Register */
extern volatile unsigned int IC7CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC7CONbits __attribute__((__sfr__));
/* IC8BUF: Input Capture 8 Buffer */
extern volatile unsigned int IC8BUF __attribute__((__sfr__));
/* IC8CON: Input Capture 8 Control Register */
extern volatile unsigned int IC8CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC8CONbits __attribute__((__sfr__));
/* --------------------------------------- */
/* Output Compare/PWM register definitions */
/* --------------------------------------- */
/* Generic structure of entire SFR area for each Output Compare module */
typedef struct tagOC {
unsigned int ocxrs;
unsigned int ocxr;
unsigned int ocxcon;
} OC, *POC;
/* SFR blocks for each Output Compare module */
extern volatile OC OC1 __attribute__((__sfr__));
extern volatile OC OC2 __attribute__((__sfr__));
extern volatile OC OC3 __attribute__((__sfr__));
extern volatile OC OC4 __attribute__((__sfr__));
/* Generic structure for Output Compare Control Registers */
typedef struct tagOCxCONBITS {
unsigned OCM :3;
unsigned OCTSEL :1;
unsigned OCFLT :1;
unsigned :8;
unsigned OCSIDL :1;
unsigned :2;
} OCxCONBITS;
/* OC1RS: Output Compare 1 Secondary Register */
extern volatile unsigned int OC1RS __attribute__((__sfr__));
/* OC1R: Output Compare 1 Main Register */
extern volatile unsigned int OC1R __attribute__((__sfr__));
/* OC1CON: Output Compare 1 Control Register */
extern volatile unsigned int OC1CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC1CONbits __attribute__((__sfr__));
/* OC2RS: Output Compare 2 Secondary Register */
extern volatile unsigned int OC2RS __attribute__((__sfr__));
/* OC2R: Output Compare 2 Main Register */
extern volatile unsigned int OC2R __attribute__((__sfr__));
/* OC2CON: Output Compare 2 Control Register */
extern volatile unsigned int OC2CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC2CONbits __attribute__((__sfr__));
/* OC3RS: Output Compare 3 Secondary Register */
extern volatile unsigned int OC3RS __attribute__((__sfr__));
/* OC3R: Output Compare 3 Main Register */
extern volatile unsigned int OC3R __attribute__((__sfr__));
/* OC3CON: Output Compare 3 Control Register */
extern volatile unsigned int OC3CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC3CONbits __attribute__((__sfr__));
/* OC4RS: Output Compare 4 Secondary Register */
extern volatile unsigned int OC4RS __attribute__((__sfr__));
/* OC4R: Output Compare 4 Main Register */
extern volatile unsigned int OC4R __attribute__((__sfr__));
/* OC4CON: Output Compare 4 Control Register */
extern volatile unsigned int OC4CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC4CONbits __attribute__((__sfr__));
/* -------------------------------------- */
/* Motor Control PWM register definitions */
/* -------------------------------------- */
/* PTCON: PWM Timerbase Control Register */
extern volatile unsigned int PTCON __attribute__((__sfr__));
typedef struct tagPTCONBITS {
unsigned PTMOD :2;
unsigned PTCKPS :2;
unsigned PTOPS :4;
unsigned :5;
unsigned PTSIDL :1;
unsigned :1;
unsigned PTEN :1;
} PTCONBITS;
extern volatile PTCONBITS PTCONbits __attribute__((__sfr__));
/* PTMR: PWM Timebase Count Register */
extern volatile unsigned int PTMR __attribute__((__sfr__));
typedef struct tagPTMRBITS {
unsigned PTMR :15;
unsigned PTDIR :1;
} PTMRBITS;
extern volatile PTMRBITS PTMRbits __attribute__((__sfr__));
/* PTPER: PWM Timebase Period Register */
extern volatile unsigned int PTPER __attribute__((__sfr__));
typedef struct tagPTPERBITS {
unsigned PTPER :15;
unsigned :1;
} PTPERBITS;
extern volatile PTPERBITS PTPERbits __attribute__((__sfr__));
/* SEVTCMP: Special Event Compare Count Register */
extern volatile unsigned int SEVTCMP __attribute__((__sfr__));
typedef struct tagSEVTCMPBITS {
unsigned SEVTCMP:15;
unsigned SEVTDIR:1;
} SEVTCMPBITS;
extern volatile SEVTCMPBITS SEVTCMPbits __attribute__((__sfr__));
/* PWMCON1: PWM Control Register 1 */
extern volatile unsigned int PWMCON1 __attribute__((__sfr__));
typedef struct tagPWMCON1BITS {
unsigned PEN1L :1;
unsigned PEN2L :1;
unsigned PEN3L :1;
unsigned :1;
unsigned PEN1H :1;
unsigned PEN2H :1;
unsigned PEN3H :1;
unsigned :1;
unsigned PMOD1 :1;
unsigned PMOD2 :1;
unsigned PMOD3 :1;
unsigned :5;
} PWMCON1BITS;
extern volatile PWMCON1BITS PWMCON1bits __attribute__((__sfr__));
/* PWMCON2: PWM Control Register 2 */
extern volatile unsigned int PWMCON2 __attribute__((__sfr__));
typedef struct tagPWMCON2BITS {
unsigned UDIS :1;
unsigned OSYNC :1;
unsigned IUE :1;
unsigned :5;
unsigned SEVOPS :4;
unsigned :4;
} PWMCON2BITS;
extern volatile PWMCON2BITS PWMCON2bits __attribute__((__sfr__));
/* DTCON1: PWM Dead Time Control Register 1 */
extern volatile unsigned int DTCON1 __attribute__((__sfr__));
typedef struct tagDTCON1BITS {
unsigned DTA :6;
unsigned DTAPS :2;
unsigned :8;
} DTCON1BITS;
extern volatile DTCON1BITS DTCON1bits __attribute__((__sfr__));
/* FLTACON: PWM Fault Input A Control Register */
extern volatile unsigned int FLTACON __attribute__((__sfr__));
typedef struct tagFLTACONBITS {
unsigned FAEN1 :1;
unsigned FAEN2 :1;
unsigned FAEN3 :1;
unsigned :4;
unsigned FLTAM :1;
unsigned FAOV1L :1;
unsigned FAOV1H :1;
unsigned FAOV2L :1;
unsigned FAOV2H :1;
unsigned FAOV3L :1;
unsigned FAOV3H :1;
unsigned :2;
} FLTACONBITS;
extern volatile FLTACONBITS FLTACONbits __attribute__((__sfr__));
/* OVDCON: PWM Override Control Register */
extern volatile unsigned int OVDCON __attribute__((__sfr__));
typedef struct tagOVDCONBITS {
unsigned POUT1L :1;
unsigned POUT1H :1;
unsigned POUT2L :1;
unsigned POUT2H :1;
unsigned POUT3L :1;
unsigned POUT3H :1;
unsigned :2;
unsigned POVD1L :1;
unsigned POVD1H :1;
unsigned POVD2L :1;
unsigned POVD2H :1;
unsigned POVD3L :1;
unsigned POVD3H :1;
unsigned :2;
} OVDCONBITS;
extern volatile OVDCONBITS OVDCONbits __attribute__((__sfr__));
/* PDC1: PWM Duty Cycle Register 1 */
extern volatile unsigned int PDC1 __attribute__((__sfr__));
/* PDC2: PWM Duty Cycle Register 2 */
extern volatile unsigned int PDC2 __attribute__((__sfr__));
/* PDC3: PWM Duty Cycle Register 3 */
extern volatile unsigned int PDC3 __attribute__((__sfr__));
/* ------------------------ */
/* I2C register definitions */
/* ------------------------ */
/* I2CRCV: I2C Receive Register */
extern volatile unsigned char I2CRCV __attribute__((__sfr__));
typedef struct tagI2CRCVBITS {
unsigned I2CRCV0:1;
unsigned I2CRCV1:1;
unsigned I2CRCV2:1;
unsigned I2CRCV3:1;
unsigned I2CRCV4:1;
unsigned I2CRCV5:1;
unsigned I2CRCV6:1;
unsigned I2CRCV7:1;
} I2CRCVBITS;
extern volatile I2CRCVBITS I2CRCVbits __attribute__((__sfr__));
/* I2CTRN: I2C Transmit Register */
extern volatile unsigned char I2CTRN __attribute__((__sfr__));
typedef struct tagI2CTRNBITS {
unsigned I2CTRN0:1;
unsigned I2CTRN1:1;
unsigned I2CTRN2:1;
unsigned I2CTRN3:1;
unsigned I2CTRN4:1;
unsigned I2CTRN5:1;
unsigned I2CTRN6:1;
unsigned I2CTRN7:1;
} I2CTRNBITS;
extern volatile I2CTRNBITS I2CTRNbits __attribute__((__sfr__));
/* I2CBRG: I2C Baud Rate Generator Register */
extern volatile unsigned int I2CBRG __attribute__((__sfr__));
typedef struct tagI2CBRGBITS {
unsigned I2CBRG :9;
unsigned :7;
} I2CBRGBITS;
extern volatile I2CBRGBITS I2CBRGbits __attribute__((__sfr__));
/* I2CCON: I2C Control Register */
extern volatile unsigned int I2CCON __attribute__((__sfr__));
typedef struct tagI2CCONBITS {
unsigned SEN :1;