🔭 Currently contributing to Network on Chip (NoC) development in XiangShan-Nanhu Team. Still new to NoC and learning along the way.
| 🎓 M.Sc. | Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences |
| 🎓 B.Sc. | Computer Science and Technology, University of Chinese Academy of Sciences |
| 💻 Tech | Computer architecture, agile hardware design, hardware security, FPGA SoCs, and low-level system software |
| 🌐 Interests | Almost everything, especially surfing on Internet, boardening horizons :) |
| Project | Description |
|---|---|
| DBChecker | SoC-level I/O security mechanism based on DMA request checking. |
| DASICS | Hardware-assisted, fine-grained in-process isolation for RISC-V processors. |
| NEXST | Linux-capable Nanhu FPGA SoCs with DDR4, PCIe, and Ethernet. (Open-source Ver.) |
| SmartNIC | A modular 100 Gbps FPGA SmartNIC built with Chisel and DPDK. |
| CCoreOS | A lightweight RISC-V operating system kernel written from scratch in C. |
- Worked across processor microarchitecture, RTL, FPGA implementation, Linux drivers, and user-space software.
- Contributed to several generations of RISC-V processors and an associated silicon project.
- National second prize in an operating-system kernel implementation competition, ranked first within the prize tier.
🌱 Learning · Building · Exploring the hardware/software boundary