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ErickOF
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MinComputerARMv4
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MinComputerARMv4
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Processorv2
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MinComputerARMv4
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Processorv2
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Name
Name
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Last commit date
parent directory
..
db
db
incremental_db
incremental_db
output_files
output_files
simulation/
modelsim
simulation/
modelsim
ALU.sv
ALU.sv
ALU.sv.bak
ALU.sv.bak
ARMStruct.sv
ARMStruct.sv
ARMStruct.sv.bak
ARMStruct.sv.bak
BombRegister.sv
BombRegister.sv
ControlUnit.sv
ControlUnit.sv
ControlUnit.sv.bak
ControlUnit.sv.bak
EnemiesRegister.sv
EnemiesRegister.sv
EnemiesRegister.sv.bak
EnemiesRegister.sv.bak
FlipFlop.sv
FlipFlop.sv
HEX.txt
HEX.txt
HEX.txt.bak
HEX.txt.bak
KeyboardDriver.sv
KeyboardDriver.sv
KeyboardDriver_testbench.sv
KeyboardDriver_testbench.sv
KeyboardRegister.sv
KeyboardRegister.sv
Processor.qpf
Processor.qpf
Processor.qsf
Processor.qsf
Processor.qws
Processor.qws
Processor_assignment_defaults.qdf
Processor_assignment_defaults.qdf
Processor_nativelink_simulation.rpt
Processor_nativelink_simulation.rpt
README.md
README.md
Substractor.sv
Substractor.sv
Substractor_nBits.sv
Substractor_nBits.sv
Substractor_nBits.sv.bak
Substractor_nBits.sv.bak
addressingDecoder.sv
addressingDecoder.sv
and_gate.sv
and_gate.sv
and_gate.sv.bak
and_gate.sv.bak
arithmeticALU.sv
arithmeticALU.sv
arithmeticALU.sv.bak
arithmeticALU.sv.bak
bankReg.sv
bankReg.sv
bankReg.sv.bak
bankReg.sv.bak
bankRegTB.sv
bankRegTB.sv
bitextender.sv
bitextender.sv
bitextenderTB.sv
bitextenderTB.sv
c5_pin_model_dump.txt
c5_pin_model_dump.txt
comparator.sv
comparator.sv
comparator.sv.bak
comparator.sv.bak
condCheck.sv
condCheck.sv
condLogic.sv
condLogic.sv
condLogic.sv.bak
condLogic.sv.bak
dataMem.sv
dataMem.sv
dataMem.sv.bak
dataMem.sv.bak
dataMemTB.sv
dataMemTB.sv
dataMemTB.sv.bak
dataMemTB.sv.bak
datapath.sv
datapath.sv
datapath.sv.bak
datapath.sv.bak
decoder.sv
decoder.sv
decoder.sv.bak
decoder.sv.bak
flag_generator.sv
flag_generator.sv
flag_generator.sv.bak
flag_generator.sv.bak
fulladder.sv
fulladder.sv
fulladder.sv.bak
fulladder.sv.bak
instructionMem.sv
instructionMem.sv
instructionMem.sv.bak
instructionMem.sv.bak
instructionMemTB.sv
instructionMemTB.sv
logicALU.sv
logicALU.sv
logicALU.sv.bak
logicALU.sv.bak
memfile.dat
memfile.dat
memfile.hex
memfile.hex
memfile.mem
memfile.mem
memfile.txt
memfile.txt
mux2x1.sv
mux2x1.sv
mux2x1.sv.bak
mux2x1.sv.bak
mux2x1_nBits.sv
mux2x1_nBits.sv
mux2x1_nBits.sv.bak
mux2x1_nBits.sv.bak
mux4x1.sv
mux4x1.sv
mux4x1.sv.bak
mux4x1.sv.bak
mux4x1Selector.sv
mux4x1Selector.sv
mux4x1Selector.sv.bak
mux4x1Selector.sv.bak
mux_not.sv
mux_not.sv
mux_not.sv.bak
mux_not.sv.bak
mux_result.sv
mux_result.sv
mux_result.sv.bak
mux_result.sv.bak
or_gate.sv
or_gate.sv
or_gate.sv.bak
or_gate.sv.bak
regDecoder.sv
regDecoder.sv
sar.sv
sar.sv
sar.sv.bak
sar.sv.bak
sc.sv
sc.sv
sc.sv.bak
sc.sv.bak
sll.sv
sll.sv
sll.sv.bak
sll.sv.bak
slr.sv
slr.sv
slr.sv.bak
slr.sv.bak
top.sv
top.sv
top.sv.bak
top.sv.bak
topTB.sv
topTB.sv
topTB.sv.bak
topTB.sv.bak
xor_gate.sv
xor_gate.sv
xor_gate.sv.bak
xor_gate.sv.bak
View all files
README.md
ARMv4 Processor
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