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Commits on Nov 20, 2019

• Test

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• Test

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• Test

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• Test

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• Add files via upload

  reiracm

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• Delete instructionMemTB.sv

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• Delete dataMemTB.sv.bak

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• Delete dataMemTB.sv

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• Delete bankRegTB.sv

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• Add files via upload

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• Merge remote-tracking branch 'origin/master'

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• Controller update 2.

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• Single Cycle Processor. Works

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• Processor v2. Test

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• Add files via upload

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• Update arithmeticALU.sv

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• Update logicALU.sv

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• Update ALU.sv

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• Update Substractor.sv

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• Merge remote-tracking branch 'origin/master'

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• Controller update added.

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• wires were added

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• Add files via upload

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• Update top.sv

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• Update ALU.sv

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• Merge remote-tracking branch 'origin/master'

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• Add files via upload

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• Update top.sv

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• Update datapath.sv

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• Update ALU.sv

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• Update ALU.sv

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• Update ARMStruct.sv

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• Update instructionMem.sv

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• Processor v2. Read instruction memory

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• Processor v2

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