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black formatting Signed-off-by: Jeff Ng <[email protected]>
added unit and flow tests
black re-formatting Signed-off-by: Jeff Ng <[email protected]>
refactored export methods
Signed-off-by: Vitor Bandeira <[email protected]>
Signed-off-by: Jeff Ng <[email protected]>
fixed coverage instrumentation more cleanup and code coverage comment updates and parse_input.py removal Signed-off-by: Jeff Ng <[email protected]>
Signed-off-by: Jeff Ng <[email protected]>
fixed snapping which was creating off-grid pins added calc_y_step unit test + black formatting Signed-off-by: Jeff Ng <[email protected]>
updated flow test to test add height; black formatting added rect_pin_mode for tight pin situations fixed track_count calculation if spare_tracks is dead on fixed we_in hardcoding in liberty + added hooks for future spreadsheet input removed comma from last pin in Verilog list Signed-off-by: Jeff Ng <[email protected]>
updated tests for LEF changes fixed verilog/sv output updated liberty to new infra black reformatting Signed-off-by: Jeff Ng <[email protected]>
Signed-off-by: Jeff Ng <[email protected]>
Signed-off-by: Jeff Ng <[email protected]>
The simulation model for SP memories wasn't describing a functional memory as on a write it was only setting bits, never clearing them. Fix the write statement. The bitwise OR operation may have been a remnant of a write mask. Before commit 0fb7f8c ("Re-factored fakeram to support sp/dp ram/regfile") there was a commented-out line: # V_file.write(' mem[addr_in] <= (wd_in & w_mask_in) | (mem[addr_in] & ~w_mask_in);\n') Signed-off-by: Martin Povišer <[email protected]>
Signed-off-by: Jeff Ng <[email protected]>
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Fixed warnings/errors relating to RE strings that weren't marked as raw.