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malibertymaliberty
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Merge pull request #1 from jeffng-or/unit-test
added unit and flow tests
2 parents d5d7529 + 7125a37 commit 7441c5d

18 files changed

+1345
-835
lines changed

‎.gitignore‎

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utils/__pycache__
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results
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*~
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.coverage
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htmlcov

‎__init__.py‎

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# To get relative imports to work
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import os, sys; sys.path.append(os.path.dirname(os.path.realpath(__file__)))

‎run.py‎

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#!/usr/bin/env python3
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import os
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import sys
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import json
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import argparse
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from pathlib import Path
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from utils.class_process import Process
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from utils.class_memory import Memory
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from utils.create_lib import create_lib
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from utils.create_lef import create_lef
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from utils.create_verilog import create_verilog
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#from utils.generate_verilog import generate_verilog_bb
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################################################################################
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# RUN GENERATOR
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# found in the JSON configuration file.
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################################################################################
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def get_args() -> argparse.Namespace:
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"""
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Get command line arguments
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)
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parser.add_argument("config", help="JSON configuration file")
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parser.add_argument(
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"--output_dir", action="store", help="Output directory ", required=False, default=None
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"--output_dir",
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action="store",
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help="Output directory ",
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required=False,
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default=None,
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)
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return parser.parse_args()
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def main ( args : argparse.Namespace):
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def ensure_results_dir(output_dir, memory_name):
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if output_dir: # Output dir was set by command line option
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p = str(Path(output_dir).expanduser().resolve(strict=False))
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results_dir = os.sep.join([p, memory_name])
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else:
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results_dir = os.sep.join([os.getcwd(), "results", memory_name])
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if not os.path.exists(results_dir):
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os.makedirs(results_dir)
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return results_dir
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def main(args: argparse.Namespace):
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# Load the JSON configuration file
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with open(args.config, "r") as fid:
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raw = [line.strip() for line in fid if not line.strip().startswith("#")]
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json_data = json.loads("\n".join(raw))
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# Load the JSON configuration file
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with open(args.config, 'r') as fid:
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raw = [line.strip() for line in fid if not line.strip().startswith('#')]
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json_data = json.loads('\n'.join(raw))
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# Create a process object (shared by all srams)
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process = Process(json_data)
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# Create a process object (shared by all srams)
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process = Process(json_data)
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# Go through each sram and generate the lib, lef and v files
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for sram_data in json_data["srams"]:
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memory = Memory(process, sram_data)
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results_dir = ensure_results_dir(args.output_dir, memory.name)
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create_lib(memory, results_dir)
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create_lef(memory, results_dir)
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create_verilog(memory, results_dir)
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# Go through each sram and generate the lib, lef and v files
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for sram_data in json_data['srams']:
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memory = Memory(process, sram_data, args.output_dir)
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create_lib(memory)
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create_lef(memory)
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create_verilog(memory)
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### Entry point
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if __name__ == '__main__':
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args = get_args()
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main( args )
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if __name__ == "__main__":
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args = get_args()
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main(args)

‎test/.gitignore‎

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*~
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#*#
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.#*
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__pycache__
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results

‎test/__init__.py‎

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# To get relative imports to work
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import os, sys; sys.path.append(os.path.dirname(os.path.realpath(__file__)))
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‎test/flow_test.py‎

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#!/usr/bin/env python3
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import re
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import os
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import math
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import shutil
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import unittest
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import subprocess
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class FlowTest(unittest.TestCase):
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""" Flow test for fakeram """
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def setUp(self):
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"""Sets up paths and REs to validate results"""
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self._test_dir = os.path.abspath(os.path.dirname(__file__));
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self._script_dir = os.path.abspath(os.path.join(self._test_dir, ".."))
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self._exec = os.path.join(self._script_dir, "run.py")
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self._results_dir = os.path.join(self._test_dir, "results")
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if os.path.isdir(self._results_dir):
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shutil.rmtree(self._results_dir)
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self._macro_re = re.compile("^MACRO\s+(\S+)")
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self._size_re = re.compile("^\s+SIZE\s+(\S+)\s+BY\s+(\S+)")
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self._start_pin_re = re.compile("^\s+PIN\s+(\S+)")
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self._macro_name_re = re.compile("\S+_(\d+)x(\d+)")
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def _getLefPin(self, fh, pin_name):
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""" Extracts data for given LEF pin and returns it in a dict """
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31+
pin_data = {}
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end_line = " END " + pin_name
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while True:
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line = fh.readline()
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if not line: # pragma: no cover
36+
return pin_data
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line = line.rstrip()
38+
if line == end_line:
39+
return pin_data
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elif line == " PORT":
41+
line = fh.readline()
42+
pin_data["layer"] = line.split()[1]
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line = fh.readline()
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pin_data["rect"] = list(map(float, line.split()[1:-1]))
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46+
def _getLefData(self, ram_file):
47+
""" Extracts data from LEF and returns it in a dict """
48+
49+
lef_data = {"pins": {}}
50+
with open(ram_file, "r") as fh:
51+
for line in fh:
52+
result = self._macro_re.match(line)
53+
if result:
54+
lef_data["macro_name"] = result.group(1)
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else:
56+
result = self._size_re.match(line)
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if result:
58+
lef_data["width"] = result.group(1)
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lef_data["height"] = result.group(2)
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else:
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result = self._start_pin_re.match(line)
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if result:
63+
pin_name = result.group(1)
64+
lef_data["pins"][pin_name] = self._getLefPin(fh, pin_name)
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return lef_data
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67+
def _checkPinShape(self, pin_name, pin_data, current_x, current_y, pin_width,
68+
layer_name):
69+
self.assertEqual(pin_data["layer"], layer_name,
70+
f"{pin_name}'s layer is not {layer_name}: {pin_data['layer']}")
71+
expected_rect = [ current_x, round(current_y, 3), current_x + pin_width, round(current_y + pin_width, 3) ]
72+
self.assertListEqual(expected_rect, pin_data["rect"],
73+
f"{pin_name}'s rect is not {expected_rect}: {pin_data['rect']}")
74+
75+
def _checkLef(self, ram_file, mem_width, mem_depth):
76+
""" Checks the LEF data against expected values for a given RAM """
77+
78+
lef_data = self._getLefData(ram_file)
79+
self.assertEqual(lef_data["macro_name"], "fakeram7_2048x39")
80+
self.assertEqual(lef_data["width"], "20.330")
81+
self.assertEqual(lef_data["height"], "166.600")
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pin_layer = "M4"
83+
pin_width = 0.024 # from config
84+
pin_spacing = 1.776 # config pin_pitch * calculated track count
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pin_group_spacing = 1.008 # config pin pitch * extra tracks
86+
read_pin_ct = write_pin_ct = mem_depth
87+
write_enable_ct = read_enable_ct = clk_ct = 1
88+
addr_pin_ct = math.log2(mem_width)
89+
power_pin_ct = 2
90+
total_pin_ct = read_pin_ct + write_pin_ct + write_enable_ct + read_enable_ct + clk_ct + addr_pin_ct + power_pin_ct
91+
self.assertEqual(len(lef_data["pins"].keys()), total_pin_ct)
92+
read_pins = [key for key in lef_data["pins"] if key.startswith("rd_out")]
93+
write_pins = [key for key in lef_data["pins"] if key.startswith("wd_in")]
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addr_pins = [key for key in lef_data["pins"] if key.startswith("addr_in")]
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self.assertEqual(len(read_pins), read_pin_ct)
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self.assertEqual(len(write_pins), write_pin_ct)
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self.assertEqual(len(addr_pins), addr_pin_ct)
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ct = 0
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current_x = 0
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current_y = pin_width * 2
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for pin_name in read_pins:
102+
self._checkPinShape(pin_name, lef_data["pins"][pin_name], current_x,
103+
current_y, pin_width, pin_layer)
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ct += 1
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current_y += pin_spacing
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current_y += pin_group_spacing
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for pin_name in write_pins:
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self._checkPinShape(pin_name, lef_data["pins"][pin_name], current_x,
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current_y, pin_width, pin_layer)
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ct += 1
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current_y += pin_spacing
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current_y += pin_group_spacing
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for pin_name in addr_pins:
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self._checkPinShape(pin_name, lef_data["pins"][pin_name], current_x,
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current_y, pin_width, pin_layer)
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current_y += pin_spacing
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current_y += pin_group_spacing
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self._checkPinShape("we_in", lef_data["pins"]["we_in"], current_x,
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current_y, pin_width, pin_layer)
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current_y += pin_spacing
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self._checkPinShape("ce_in", lef_data["pins"]["ce_in"], current_x,
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current_y, pin_width, pin_layer)
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current_y += pin_spacing
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self._checkPinShape("clk", lef_data["pins"]["clk"], current_x,
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current_y, pin_width, pin_layer)
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current_y += pin_spacing
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# Skip checking power pins
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def _checkResultsDir(self):
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""" Checks that the expected RAMs were generated """
131+
expected_ram_list = [
132+
"fakeram7_2048x39",
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"fakeram7_256x32",
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"fakeram7_256x34",
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"fakeram7_64x21",
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"fakeram_256x128",
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"fakeram_256x64",
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"fakeram_32x46",
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"fakeram_512x8",
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"fakeram_64x20",
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"fakeram_64x22",
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]
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self.assertTrue(os.path.isdir(self._results_dir))
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self.assertListEqual(sorted(os.listdir(self._results_dir)),
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expected_ram_list)
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ct = 0
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for ram_name in expected_ram_list:
148+
lef_file = os.path.join(self._results_dir, ram_name,
149+
ram_name + ".lef")
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verilog_file = os.path.join(self._results_dir, ram_name,
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ram_name + ".v")
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liberty_file = os.path.join(self._results_dir, ram_name,
153+
ram_name + ".lib")
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self.assertTrue(os.path.exists(lef_file),
155+
f"{lef_file} doesn't exist")
156+
self.assertTrue(os.path.exists(verilog_file),
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f"{verilog_file} doesn't exist")
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self.assertTrue(os.path.exists(liberty_file),
159+
f"{liberty_file} doesn't exist")
160+
if ct == 0:
161+
results = self._macro_name_re.match(ram_name)
162+
mem_width = int(results.group(1))
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mem_depth = int(results.group(2))
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self._checkLef(lef_file, mem_width, mem_depth)
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ct += 1
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def test_example_input(self):
168+
""" Tests the example input run """
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170+
cmd = self._exec + " " + os.path.join(self._script_dir, "example_input_file.cfg") + " --output_dir " + self._results_dir
171+
out = subprocess.run(cmd, check=True, shell=True)
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self.assertEqual(out.returncode, 0)
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self._checkResultsDir()
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if __name__ == "__main__":
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unittest.main()
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‎test/macro_dim_test.py‎

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#!/usr/bin/env python3
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import os
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import sys
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import unittest
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sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "utils")))
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from class_process import Process
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from test_utils import TestUtils
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import area
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12+
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class MacroDimTest(unittest.TestCase):
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"""Unit test for get_macro_dimensions method"""
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def setUp(self):
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"""Sets up process object used by test methods"""
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self._process = Process(TestUtils.get_base_process_data())
20+
# delta for use when comparing floats
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self._delta = 0.01
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def test_macro_dim(self):
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"""
25+
Tests basic macro dimension calculation based on three bank
26+
configurations
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"""
28+
29+
banks = [1, 2, 4]
30+
base_height = 663.552
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base_width = 5.054
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for num_banks in banks:
33+
sram_data = {
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"width": 39,
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"depth": 2048,
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"banks": num_banks,
37+
}
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(height, width) = area.get_macro_dimensions(self._process, sram_data)
39+
exp_height = base_height / num_banks
40+
exp_width = base_width * num_banks
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self.assertAlmostEqual(height, exp_height, delta=self._delta)
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self.assertAlmostEqual(width, exp_width, delta=self._delta)
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def test_macro_dim_invalid_banks(self):
45+
"""Tests detection that an invalid bank value was given"""
46+
47+
sram_data = {
48+
"width": 39,
49+
"depth": 2048,
50+
"banks": 8,
51+
}
52+
with self.assertRaises(Exception):
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(height, width) = area.get_macro_dimensions(self._process, sram_data)
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if __name__ == "__main__":
57+
unittest.main()

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