11#!/usr/bin/env python3
22
3- import os
43import sys
5- import json
64import argparse
7- from pathlib import Path
85
6+ from utils .run_utils import RunUtils
97from utils .class_process import Process
10- from utils .class_memory import Memory
11-
12- from utils .create_lib import create_lib
13- from utils .create_lef import create_lef
14- from utils .create_verilog import create_verilog
15-
16- ################################################################################
17- # RUN GENERATOR
18- #
19- # This is the main part of the script. It will read in the JSON configuration
20- # file, create a Cacti configuration file, run Cacti, extract the data from
21- # Cacti, and then generate the timing, physical and logical views for each SRAM
22- # found in the JSON configuration file.
23- ################################################################################
8+ from utils .memory_factory import MemoryFactory
9+ from utils .timing_data import TimingData
2410
2511
2612def get_args () -> argparse .Namespace :
@@ -29,9 +15,8 @@ def get_args() -> argparse.Namespace:
2915 """
3016 parser = argparse .ArgumentParser (
3117 description = """
32- BSG Black-box SRAM Generator --
3318 This project is designed to generate black-boxed SRAMs for use in CAD
34- flows where either an SRAM generator is not avaible or doesn't
19+ flows where either an SRAM generator is not available or doesn't
3520 exist. """
3621 )
3722 parser .add_argument ("config" , help = "JSON configuration file" )
@@ -40,39 +25,49 @@ def get_args() -> argparse.Namespace:
4025 action = "store" ,
4126 help = "Output directory " ,
4227 required = False ,
43- default = None ,
28+ default = "results" ,
4429 )
4530 return parser .parse_args ()
4631
4732
48- def ensure_results_dir (output_dir , memory_name ):
49- if output_dir : # Output dir was set by command line option
50- p = str (Path (output_dir ).expanduser ().resolve (strict = False ))
51- results_dir = os .sep .join ([p , memory_name ])
52- else :
53- results_dir = os .sep .join ([os .getcwd (), "results" , memory_name ])
54- if not os .path .exists (results_dir ):
55- os .makedirs (results_dir )
56- return results_dir
33+ def get_memory_type (json_data ):
34+ if "memory_type" in json_data :
35+ return json_data ["memory_type" ]
36+ return "RAM"
5737
5838
59- def main (args : argparse .Namespace ):
39+ def get_port_config (json_data ):
40+ if "port_configuration" in json_data :
41+ return json_data ["port_configuration" ]
42+ return "SP"
6043
61- # Load the JSON configuration file
62- with open (args .config , "r" ) as fid :
63- raw = [line .strip () for line in fid if not line .strip ().startswith ("#" )]
64- json_data = json .loads ("\n " .join (raw ))
6544
45+ def main (args : argparse .Namespace ):
46+ json_data = RunUtils .get_config (args .config )
6647 # Create a process object (shared by all srams)
6748 process = Process (json_data )
49+ timing_data = TimingData (json_data )
50+
51+ memory_type = get_memory_type (json_data )
52+ port_config = get_port_config (json_data )
6853
6954 # Go through each sram and generate the lib, lef and v files
7055 for sram_data in json_data ["srams" ]:
71- memory = Memory (process , sram_data )
72- results_dir = ensure_results_dir (args .output_dir , memory .name )
73- create_lib (memory , results_dir )
74- create_lef (memory , results_dir )
75- create_verilog (memory , results_dir )
56+ name = str (sram_data ["name" ])
57+ width_in_bits = int (sram_data ["width" ])
58+ depth = int (sram_data ["depth" ])
59+ num_banks = int (sram_data ["banks" ])
60+ memory = MemoryFactory .create (
61+ name ,
62+ width_in_bits ,
63+ depth ,
64+ num_banks ,
65+ memory_type ,
66+ port_config ,
67+ process ,
68+ timing_data ,
69+ )
70+ RunUtils .write_memory (memory , args .output_dir )
7671
7772
7873### Entry point
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